component

TMS320F28053PNS

Public Made by Adom

by adom

Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllerstms320f28053pnsfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 19d ago
viewers tms320f28053pns: viewers · Ray 19d ago
package.json Publish 0.1.0 · Ray 19d ago
page.json Set visibility: public · Ray 19d ago
README.md Initial commit: component/tms320f28053pns · Ray 19d ago
tms320f28053pns-etched.glb tms320f28053pns: factory component page (tier=lcsc) · Ray 19d ago
tms320f28053pns-etched.step tms320f28053pns: factory component page (tier=lcsc) · Ray 19d ago
tms320f28053pns-hero.glb tms320f28053pns: hero GLB from the etched model (keeps the MPN mark) · Ray 18d ago
tms320f28053pns-hero.overlay.json Publish 0.1.0 · Ray 19d ago
tms320f28053pns.glb Publish 0.1.0 · Ray 19d ago
tms320f28053pns.kicad_mod Publish 0.1.0 · Ray 19d ago
tms320f28053pns.kicad_sym Publish 0.1.0 · Ray 19d ago
tms320f28053pns.lbr Publish 0.1.0 · Ray 19d ago
tms320f28053pns.step Publish 0.1.0 · Ray 19d ago

TMS320F28053PNS

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)

TMS320F28053PNS from Texas Instruments, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO22 bidirectional General-purpose I/O 22 with alternates EQEP1S (I/O) and SCITXDB (output); inputs are not 5-V tolerant.
2 GPIO32 bidirectional General-purpose I/O 32 with alternates SDAA (I2C data, open-drain), EPWMSYNCI (input) and EQEP1S (I/O); inputs are not 5-V tolerant.
3 GPIO33 bidirectional General-purpose I/O 33 with alternates SCLA (I2C clock, open-drain), EPWMSYNCO (output) and EQEP1I (I/O).
4 GPIO24 bidirectional General-purpose I/O 24 with internal pullup enabled by default; alternates ECAP1 (I/O) and EPWM7A (output).
5 GPIO42 bidirectional General-purpose I/O 42 with internal pullup enabled by default; alternates EPWM7B, SCITXDC and CTRIPM1OUT (outputs).
6 VDD power_in CPU and logic digital power pin; when the internal VREG is used, place one 1.2-µF capacitor between each VDD pin and ground (higher values allowed).
7 VSS power_in Digital ground pin.
8 XRS bidirectional Device reset input and watchdog reset output (open-drain with internal pullup); a 2.2 kΩ to 10 kΩ resistor to VDDIO is to be placed on it and any capacitor to VSS should be 100 nF or smaller.
9 TRST input JTAG test reset with internal pulldown; must be maintained low during normal device operation and an external pulldown resistor is required (2.2 kΩ generally adequate).
10 ADCINA5 input ADC Group A, channel 5 analog input.
11 ADCINA4 input ADC Group A, channel 4 analog input.
12 ADCINA3 input ADC Group A, channel 3 analog input (op-amp channel, associated with M1GND).
13 ADCINA2 input ADC Group A, channel 2 analog input.
14 ADCINA1 input ADC Group A, channel 1 analog input (op-amp channel, associated with M1GND).
15 M1GND power_in Ground pin for amplifier channels A1, A3 and B1.
16 ADCINB2 input ADC Group B, channel 2 analog input.
17 ADCINB1 input ADC Group B, channel 1 analog input (op-amp channel).
18 ADCINA0/VREFOUT input ADC Group A, channel 0 analog input; also serves as the voltage reference output (VREFOUT) from the buffered DAC.
19 VREFHI input ADC external reference input, used in ADC external reference mode and as the VREFOUT reference.
20 VDDA power_in Analog power pin; tie with a 2.2-µF (typical) capacitor close to the pin.
21 VSSA power_in Analog ground pin.
22 VREFLO input ADC low reference input; always tied to ground.
23 ADCINA6 input ADC Group A, channel 6 analog input (op-amp channel).
24 ADCINA7 input ADC Group A, channel 7 analog input.
25 ADCINB3 input ADC Group B, channel 3 analog input.
26 ADCINB4 input ADC Group B, channel 4 analog input (op-amp channel, associated with M2GND).
27 M2GND power_in Ground pin for amplifier channels A6, B4 and B6.
28 ADCINB5 input ADC Group B, channel 5 analog input.
29 ADCINB6 input ADC Group B, channel 6 analog input (op-amp channel).
30 ADCINB0 input ADC Group B, channel 0 analog input.
31 ADCINB7 input ADC Group B, channel 7 analog input (op-amp channel, associated with PFCGND).
32 PFCGND power_in Ground pin for amplifier channel B7.
33 GPIO27 bidirectional General-purpose I/O 27 with alternate SCITXDC (output).
34 GPIO31 bidirectional General-purpose I/O 31 with internal pullup enabled by default; alternates CANTXA, SCITXDB and EPWM7B (outputs).
35 GPIO30 bidirectional General-purpose I/O 30 with internal pullup enabled by default; alternates CANRXA (input), SCIRXDB (input) and EPWM7A (output).
36 GPIO9 bidirectional General-purpose I/O 9 with alternates EPWM5B (output) and SCITXDB (output).
37 VSS power_in Digital ground pin.
38 VDDIO power_in Digital I/O buffer and flash memory power pin; single supply source when VREG is enabled; place a decoupling capacitor on each VDDIO pin.
39 TEST2 bidirectional Test pin reserved for TI; must be left unconnected.
40 GPIO26 bidirectional General-purpose I/O 26 with alternate SCIRXDC (input).
41 GPIO29 bidirectional General-purpose I/O 29 with alternates SCITXDA (output), SCLA (I2C clock, open-drain), TZ3 (input) and CTRIPPFCOUT (output).
42 GPIO28 bidirectional General-purpose I/O 28 with alternates SCIRXDA (input), SDAA (I2C data, open-drain) and TZ2 (input).
43 GPIO18 bidirectional General-purpose I/O 18 with alternates SPICLKA (I/O), SCITXDB (output) and XCLKOUT; XCLKOUT is SYSCLKOUT divided by 1, 2 or 4, resets to SYSCLKOUT/4 and can be turned off by setting XCLKOUTDIV to 3.
44 GPIO17 bidirectional General-purpose I/O 17 with alternates SPISOMIA (I/O), EQEP1I (I/O), TZ3 (input) and CTRIPPFCOUT (output).
45 GPIO8 bidirectional General-purpose I/O 8 with alternates EPWM5A (output) and ADCSOCAO (output).
46 GPIO25 bidirectional General-purpose I/O 25; all alternate functions are reserved for this pin.
47 GPIO16 bidirectional General-purpose I/O 16 with alternates SPISIMOA (I/O), EQEP1S (I/O) and TZ2 (input).
48 GPIO12 bidirectional General-purpose I/O 12 with alternates TZ1 (input), CTRIPM1OUT (output) and SCITXDA (output).
49 GPIO7 bidirectional General-purpose I/O 7 with alternates EPWM4B (output) and SCIRXDA (input).
50 GPIO6 bidirectional General-purpose I/O 6 with alternates EPWM4A (output), EPWMSYNCI (input) and EPWMSYNCO (output).
51 X2 output On-chip crystal oscillator output; a quartz crystal or ceramic resonator is connected across X1 and X2, and X2 must be left unconnected if not used.
52 X1 input On-chip 1.8-V crystal oscillator input; a crystal or resonator is connected across X1 and X2, and the pin must be tied to GND if not used.
53 VSS power_in Digital ground pin.
54 VDD power_in CPU and logic digital power pin; when the internal VREG is used, place one 1.2-µF capacitor between each VDD pin and ground (higher values allowed).
55 GPIO19 bidirectional General-purpose I/O 19 with alternates XCLKIN (external oscillator input), SPISTEA (I/O), SCIRXDB (input) and ECAP1 (I/O); may glitch during power-up when the on-chip VREG is used.
56 GPIO39 bidirectional General-purpose I/O 39 with alternates SCIRXDC (input) and CTRIPPFCOUT (output).
57 GPIO38 bidirectional General-purpose I/O 38 (default XCLKIN selection) with alternates TCK (JTAG clock, internal pullup) and XCLKIN (external oscillator input); avoid enabling the XCLKIN path during JTAG debug to prevent contention with TCK, and may glitch during power-up when VREG is used.
58 GPIO37 tri_state JTAG scan out (TDO) with 8 mA drive, shifted out on the falling edge of TCK; also GPIO37, and may glitch during power-up when VREG is used.
59 GPIO35 bidirectional JTAG test data input (TDI) with internal pullup, clocked into the selected register on the rising edge of TCK; also GPIO35 and may glitch during power-up when VREG is used.
60 GPIO36 bidirectional JTAG test-mode select (TMS) with internal pullup, clocked into the TAP controller on the rising edge of TCK; also GPIO36 and may glitch during power-up when VREG is used.
61 GPIO11 bidirectional General-purpose I/O 11 with alternates EPWM6B (output) and SCIRXDB (input).
62 GPIO5 bidirectional General-purpose I/O 5 with alternates EPWM3B (output), SPISIMOA (I/O) and ECAP1 (I/O).
63 GPIO4 bidirectional General-purpose I/O 4 with alternate EPWM3A (output).
64 GPIO40 bidirectional General-purpose I/O 40 with internal pullup enabled by default; alternate EPWM7A (output).
65 GPIO10 bidirectional General-purpose I/O 10 with alternates EPWM6A (output) and ADCSOCBO (output).
66 GPIO3 bidirectional General-purpose I/O 3 with alternates EPWM2B (output) and SPISOMIA (I/O).
67 GPIO2 bidirectional General-purpose I/O 2 with alternate EPWM2A (output).
68 GPIO1 bidirectional General-purpose I/O 1 with alternates EPWM1B (output) and CTRIPM1OUT (output).
69 GPIO0 bidirectional General-purpose I/O 0 with alternate EPWM1A (output); PWM-pin pullup is not enabled at reset.
70 VDDIO power_in Digital I/O buffer and flash memory power pin; single supply source when VREG is enabled; place a decoupling capacitor on each VDDIO pin.
71 VREGENZ input Internal voltage regulator enable with internal pulldown; tie to VSS to enable the internal 1.8-V VREG, or tie to VDDIO to disable it and use an external 1.8-V supply.
72 VSS power_in Digital ground pin.
73 VDD power_in CPU and logic digital power pin; when the internal VREG is used, place one 1.2-µF capacitor between each VDD pin and ground (higher values allowed).
74 GPIO34 bidirectional General-purpose I/O 34 with alternate CTRIPPFCOUT (output); not glitch-free and may glitch during power-up when the on-chip VREG is used.
75 GPIO15 bidirectional General-purpose I/O 15 with alternates TZ1 (input), CTRIPM1OUT (output) and SCIRXDB (input).
76 GPIO13 bidirectional General-purpose I/O 13 with alternate TZ2 (input, trip zone).
77 GPIO14 bidirectional General-purpose I/O 14 with alternates TZ3 (input), CTRIPPFCOUT (output) and SCITXDB (output).
78 GPIO20 bidirectional General-purpose I/O 20 with internal pullup enabled by default; alternates EQEP1A (input), EPWM7A (output) and CTRIPM1OUT (output).
79 GPIO21 bidirectional General-purpose I/O 21 with internal pullup enabled by default; alternates EQEP1B (input) and EPWM7B (output).
80 GPIO23 bidirectional General-purpose I/O 23 with alternates EQEP1I (I/O) and SCIRXDB (input).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-80(12x12)
Category Embedded Processors & Controllers
Pins 80

CAD (KiCad official)

  • Symbol: TMS320F28053PNS
  • Footprint: Package_QFP:LQFP-80_12x12mm_P0.5mm
  • 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)
  • 3D model files: tms320f28053pns-etched.step / tms320f28053pns-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f28053pns.step / tms320f28053pns.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (159 pp, sha256 aaaaedb6c548633c, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF