component
TMS320F28053PNS
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+117@@ -0,0 +1,117 @@+# TMS320F28053PNS++**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)++TMS320F28053PNS from Texas Instruments, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GPIO22 | bidirectional | General-purpose I/O 22 with alternates EQEP1S (I/O) and SCITXDB (output); inputs are not 5-V tolerant. |+| 2 | GPIO32 | bidirectional | General-purpose I/O 32 with alternates SDAA (I2C data, open-drain), EPWMSYNCI (input) and EQEP1S (I/O); inputs are not 5-V tolerant. |+| 3 | GPIO33 | bidirectional | General-purpose I/O 33 with alternates SCLA (I2C clock, open-drain), EPWMSYNCO (output) and EQEP1I (I/O). |+| 4 | GPIO24 | bidirectional | General-purpose I/O 24 with internal pullup enabled by default; alternates ECAP1 (I/O) and EPWM7A (output). |+| 5 | GPIO42 | bidirectional | General-purpose I/O 42 with internal pullup enabled by default; alternates EPWM7B, SCITXDC and CTRIPM1OUT (outputs). |+| 6 | VDD | power_in | CPU and logic digital power pin; when the internal VREG is used, place one 1.2-µF capacitor between each VDD pin and ground (higher values allowed). |+| 7 | VSS | power_in | Digital ground pin. |+| 8 | XRS | bidirectional | Device reset input and watchdog reset output (open-drain with internal pullup); a 2.2 kΩ to 10 kΩ resistor to VDDIO is to be placed on it and any capacitor to VSS should be 100 nF or smaller. |+| 9 | TRST | input | JTAG test reset with internal pulldown; must be maintained low during normal device operation and an external pulldown resistor is required (2.2 kΩ generally adequate). |+| 10 | ADCINA5 | input | ADC Group A, channel 5 analog input. |+| 11 | ADCINA4 | input | ADC Group A, channel 4 analog input. |+| 12 | ADCINA3 | input | ADC Group A, channel 3 analog input (op-amp channel, associated with M1GND). |+| 13 | ADCINA2 | input | ADC Group A, channel 2 analog input. |+| 14 | ADCINA1 | input | ADC Group A, channel 1 analog input (op-amp channel, associated with M1GND). |+| 15 | M1GND | power_in | Ground pin for amplifier channels A1, A3 and B1. |+| 16 | ADCINB2 | input | ADC Group B, channel 2 analog input. |+| 17 | ADCINB1 | input | ADC Group B, channel 1 analog input (op-amp channel). |+| 18 | ADCINA0/VREFOUT | input | ADC Group A, channel 0 analog input; also serves as the voltage reference output (VREFOUT) from the buffered DAC. |+| 19 | VREFHI | input | ADC external reference input, used in ADC external reference mode and as the VREFOUT reference. |+| 20 | VDDA | power_in | Analog power pin; tie with a 2.2-µF (typical) capacitor close to the pin. |+| 21 | VSSA | power_in | Analog ground pin. |+| 22 | VREFLO | input | ADC low reference input; always tied to ground. |+| 23 | ADCINA6 | input | ADC Group A, channel 6 analog input (op-amp channel). |+| 24 | ADCINA7 | input | ADC Group A, channel 7 analog input. |+| 25 | ADCINB3 | input | ADC Group B, channel 3 analog input. |+| 26 | ADCINB4 | input | ADC Group B, channel 4 analog input (op-amp channel, associated with M2GND). |+| 27 | M2GND | power_in | Ground pin for amplifier channels A6, B4 and B6. |+| 28 | ADCINB5 | input | ADC Group B, channel 5 analog input. |+| 29 | ADCINB6 | input | ADC Group B, channel 6 analog input (op-amp channel). |+| 30 | ADCINB0 | input | ADC Group B, channel 0 analog input. |+| 31 | ADCINB7 | input | ADC Group B, channel 7 analog input (op-amp channel, associated with PFCGND). |+| 32 | PFCGND | power_in | Ground pin for amplifier channel B7. |+| 33 | GPIO27 | bidirectional | General-purpose I/O 27 with alternate SCITXDC (output). |+| 34 | GPIO31 | bidirectional | General-purpose I/O 31 with internal pullup enabled by default; alternates CANTXA, SCITXDB and EPWM7B (outputs). |+| 35 | GPIO30 | bidirectional | General-purpose I/O 30 with internal pullup enabled by default; alternates CANRXA (input), SCIRXDB (input) and EPWM7A (output). |+| 36 | GPIO9 | bidirectional | General-purpose I/O 9 with alternates EPWM5B (output) and SCITXDB (output). |+| 37 | VSS | power_in | Digital ground pin. |+| 38 | VDDIO | power_in | Digital I/O buffer and flash memory power pin; single supply source when VREG is enabled; place a decoupling capacitor on each VDDIO pin. |+| 39 | TEST2 | bidirectional | Test pin reserved for TI; must be left unconnected. |+| 40 | GPIO26 | bidirectional | General-purpose I/O 26 with alternate SCIRXDC (input). |+| 41 | GPIO29 | bidirectional | General-purpose I/O 29 with alternates SCITXDA (output), SCLA (I2C clock, open-drain), TZ3 (input) and CTRIPPFCOUT (output). |+| 42 | GPIO28 | bidirectional | General-purpose I/O 28 with alternates SCIRXDA (input), SDAA (I2C data, open-drain) and TZ2 (input). |+| 43 | GPIO18 | bidirectional | General-purpose I/O 18 with alternates SPICLKA (I/O), SCITXDB (output) and XCLKOUT; XCLKOUT is SYSCLKOUT divided by 1, 2 or 4, resets to SYSCLKOUT/4 and can be turned off by setting XCLKOUTDIV to 3. |+| 44 | GPIO17 | bidirectional | General-purpose I/O 17 with alternates SPISOMIA (I/O), EQEP1I (I/O), TZ3 (input) and CTRIPPFCOUT (output). |+| 45 | GPIO8 | bidirectional | General-purpose I/O 8 with alternates EPWM5A (output) and ADCSOCAO (output). |+| 46 | GPIO25 | bidirectional | General-purpose I/O 25; all alternate functions are reserved for this pin. |+| 47 | GPIO16 | bidirectional | General-purpose I/O 16 with alternates SPISIMOA (I/O), EQEP1S (I/O) and TZ2 (input). |+| 48 | GPIO12 | bidirectional | General-purpose I/O 12 with alternates TZ1 (input), CTRIPM1OUT (output) and SCITXDA (output). |+| 49 | GPIO7 | bidirectional | General-purpose I/O 7 with alternates EPWM4B (output) and SCIRXDA (input). |+| 50 | GPIO6 | bidirectional | General-purpose I/O 6 with alternates EPWM4A (output), EPWMSYNCI (input) and EPWMSYNCO (output). |+| 51 | X2 | output | On-chip crystal oscillator output; a quartz crystal or ceramic resonator is connected across X1 and X2, and X2 must be left unconnected if not used. |+| 52 | X1 | input | On-chip 1.8-V crystal oscillator input; a crystal or resonator is connected across X1 and X2, and the pin must be tied to GND if not used. |+| 53 | VSS | power_in | Digital ground pin. |+| 54 | VDD | power_in | CPU and logic digital power pin; when the internal VREG is used, place one 1.2-µF capacitor between each VDD pin and ground (higher values allowed). |+| 55 | GPIO19 | bidirectional | General-purpose I/O 19 with alternates XCLKIN (external oscillator input), SPISTEA (I/O), SCIRXDB (input) and ECAP1 (I/O); may glitch during power-up when the on-chip VREG is used. |+| 56 | GPIO39 | bidirectional | General-purpose I/O 39 with alternates SCIRXDC (input) and CTRIPPFCOUT (output). |+| 57 | GPIO38 | bidirectional | General-purpose I/O 38 (default XCLKIN selection) with alternates TCK (JTAG clock, internal pullup) and XCLKIN (external oscillator input); avoid enabling the XCLKIN path during JTAG debug to prevent contention with TCK, and may glitch during power-up when VREG is used. |+| 58 | GPIO37 | tri_state | JTAG scan out (TDO) with 8 mA drive, shifted out on the falling edge of TCK; also GPIO37, and may glitch during power-up when VREG is used. |+| 59 | GPIO35 | bidirectional | JTAG test data input (TDI) with internal pullup, clocked into the selected register on the rising edge of TCK; also GPIO35 and may glitch during power-up when VREG is used. |+| 60 | GPIO36 | bidirectional | JTAG test-mode select (TMS) with internal pullup, clocked into the TAP controller on the rising edge of TCK; also GPIO36 and may glitch during power-up when VREG is used. |+| 61 | GPIO11 | bidirectional | General-purpose I/O 11 with alternates EPWM6B (output) and SCIRXDB (input). |+| 62 | GPIO5 | bidirectional | General-purpose I/O 5 with alternates EPWM3B (output), SPISIMOA (I/O) and ECAP1 (I/O). |+| 63 | GPIO4 | bidirectional | General-purpose I/O 4 with alternate EPWM3A (output). |+| 64 | GPIO40 | bidirectional | General-purpose I/O 40 with internal pullup enabled by default; alternate EPWM7A (output). |+| 65 | GPIO10 | bidirectional | General-purpose I/O 10 with alternates EPWM6A (output) and ADCSOCBO (output). |+| 66 | GPIO3 | bidirectional | General-purpose I/O 3 with alternates EPWM2B (output) and SPISOMIA (I/O). |+| 67 | GPIO2 | bidirectional | General-purpose I/O 2 with alternate EPWM2A (output). |+| 68 | GPIO1 | bidirectional | General-purpose I/O 1 with alternates EPWM1B (output) and CTRIPM1OUT (output). |+| 69 | GPIO0 | bidirectional | General-purpose I/O 0 with alternate EPWM1A (output); PWM-pin pullup is not enabled at reset. |+| 70 | VDDIO | power_in | Digital I/O buffer and flash memory power pin; single supply source when VREG is enabled; place a decoupling capacitor on each VDDIO pin. |+| 71 | VREGENZ | input | Internal voltage regulator enable with internal pulldown; tie to VSS to enable the internal 1.8-V VREG, or tie to VDDIO to disable it and use an external 1.8-V supply. |+| 72 | VSS | power_in | Digital ground pin. |+| 73 | VDD | power_in | CPU and logic digital power pin; when the internal VREG is used, place one 1.2-µF capacitor between each VDD pin and ground (higher values allowed). |+| 74 | GPIO34 | bidirectional | General-purpose I/O 34 with alternate CTRIPPFCOUT (output); not glitch-free and may glitch during power-up when the on-chip VREG is used. |+| 75 | GPIO15 | bidirectional | General-purpose I/O 15 with alternates TZ1 (input), CTRIPM1OUT (output) and SCIRXDB (input). |+| 76 | GPIO13 | bidirectional | General-purpose I/O 13 with alternate TZ2 (input, trip zone). |+| 77 | GPIO14 | bidirectional | General-purpose I/O 14 with alternates TZ3 (input), CTRIPPFCOUT (output) and SCITXDB (output). |+| 78 | GPIO20 | bidirectional | General-purpose I/O 20 with internal pullup enabled by default; alternates EQEP1A (input), EPWM7A (output) and CTRIPM1OUT (output). |+| 79 | GPIO21 | bidirectional | General-purpose I/O 21 with internal pullup enabled by default; alternates EQEP1B (input) and EPWM7B (output). |+| 80 | GPIO23 | bidirectional | General-purpose I/O 23 with alternates EQEP1I (I/O) and SCIRXDB (input). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | LQFP-80(12x12) |+| Category | Embedded Processors & Controllers |+| Pins | 80 |++## CAD (KiCad official)++- Symbol: `TMS320F28053PNS`+- Footprint: `Package_QFP:LQFP-80_12x12mm_P0.5mm`+- 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)+- 3D model files: `tms320f28053pns-etched.step` / `tms320f28053pns-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tms320f28053pns.step` / `tms320f28053pns.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tms320f28054f) (159 pp, sha256 `aaaaedb6c548633c`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tms320f28053pns-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "tms320f28053pns",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tms320f28053pns.kicad_sym",+ "tms320f28053pns.kicad_mod",+ "tms320f28053pns.glb",+ "tms320f28053pns.step",+ "tms320f28053pns.lbr",+ "docs/hero.png",+ "docs/tms320f28053pns-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tms320f28053pns-hero.glb",+ "tms320f28053pns-hero.overlay.json"+ ],+ "component": {+ "mpn": "TMS320F28053PNS",+ "manufacturer": "Texas Instruments",+ "package": "LQFP-80(12x12)",+ "pin_count": 80,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tms320f28054f",+ "parts": {+ "symbol": "tms320f28053pns.kicad_sym",+ "footprint": "tms320f28053pns.kicad_mod",+ "model_3d": "tms320f28053pns-hero.glb",+ "model_3d_plain": "tms320f28053pns.glb",+ "model_3d_step": "tms320f28053pns-etched.step",+ "model_3d_step_plain": "tms320f28053pns.step",+ "lbr": "tms320f28053pns.lbr"+ },+ "distributor_links": {+ "lcsc": "C1339533",+ "digikey": "2156-TMS320F28053PNS-ND",+ "mouser": "595-TMS320F28053PNS"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T04:47:04Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "2156-TMS320F28053PNS-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-TMS320F28053PNS",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "GPIO22",+ "type": "bidirectional",+ "description": "General-purpose I/O 22 with alternates EQEP1S (I/O) and SCITXDB (output); inputs are not 5-V tolerant."+ },+ {+ "number": "2",+ "name": "GPIO32",+ "type": "bidirectional",+ "description": "General-purpose I/O 32 with alternates SDAA (I2C data, open-drain), EPWMSYNCI (input) and EQEP1S (I/O); inputs are not 5-V tolerant."+ },+ {+ "number": "3",+ "name": "GPIO33",+ "type": "bidirectional",+ "description": "General-purpose I/O 33 with alternates SCLA (I2C clock, open-drain), EPWMSYNCO (output) and EQEP1I (I/O)."+ },+ {+ "number": "4",+ "name": "GPIO24",+ "type": "bidirectional",+ "description": "General-purpose I/O 24 with internal pullup enabled by default; alternates ECAP1 (I/O) and EPWM7A (output)."+ },+ {+ "number": "5",+ "name": "GPIO42",+ "type": "bidirectional",+ "description": "General-purpose I/O 42 with internal pullup enabled by default; alternates EPWM7B, SCITXDC and CTRIPM1OUT (outputs)."+ },+ {+ "number": "6",+ "name": "VDD",+ "type": "power_in",+ "description": "CPU and logic digital power pin; when the internal VREG is used, place one 1.2-µF capacitor between each VDD pin and ground (higher values allowed)."+ },+ {+ "number": "7",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin."+ },+ {+ "number": "8",+ "name": "XRS",+ "type": "bidirectional",+ "description": "Device reset input and watchdog reset output (open-drain with internal pullup); a 2.2 kΩ to 10 kΩ resistor to VDDIO is to be placed on it and any capacitor to VSS should be 100 nF or smaller."+ },+ {+ "number": "9",+ "name": "TRST",+ "type": "input",+ "description": "JTAG test reset with internal pulldown; must be maintained low during normal device operation and an external pulldown resistor is required (2.2 kΩ generally adequate)."+ },+ {+ "number": "10",+ "name": "ADCINA5",+ "type": "input",+ "description": "ADC Group A, channel 5 analog input."+ },+ {+ "number": "11",+ "name": "ADCINA4",+ "type": "input",+ "description": "ADC Group A, channel 4 analog input."+ },+ {+ "number": "12",+ "name": "ADCINA3",+ "type": "input",+ "description": "ADC Group A, channel 3 analog input (op-amp channel, associated with M1GND)."+ },+ {+ "number": "13",+ "name": "ADCINA2",+ "type": "input",+ "description": "ADC Group A, channel 2 analog input."+ },+ {+ "number": "14",+ "name": "ADCINA1",+ "type": "input",+ "description": "ADC Group A, channel 1 analog input (op-amp channel, associated with M1GND)."+ },+ {+ "number": "15",+ "name": "M1GND",+ "type": "power_in",+ "description": "Ground pin for amplifier channels A1, A3 and B1."+ },+ {+ "number": "16",+ "name": "ADCINB2",+ "type": "input",+ "description": "ADC Group B, channel 2 analog input."+ },+ {+ "number": "17",+ "name": "ADCINB1",+ "type": "input",+ "description": "ADC Group B, channel 1 analog input (op-amp channel)."+ },+ {+ "number": "18",+ "name": "ADCINA0/VREFOUT",+ "type": "input",+ "description": "ADC Group A, channel 0 analog input; also serves as the voltage reference output (VREFOUT) from the buffered DAC."+ },+ {+ "number": "19",+ "name": "VREFHI",+ "type": "input",+ "description": "ADC external reference input, used in ADC external reference mode and as the VREFOUT reference."+ },+ {+ "number": "20",+ "name": "VDDA",+ "type": "power_in",+ "description": "Analog power pin; tie with a 2.2-µF (typical) capacitor close to the pin."+ },+ {+ "number": "21",+ "name": "VSSA",+ "type": "power_in",+ "description": "Analog ground pin."+ },+ {+ "number": "22",+ "name": "VREFLO",+ "type": "input",+ "description": "ADC low reference input; always tied to ground."+ },+ {+ "number": "23",+ "name": "ADCINA6",+ "type": "input",+ "description": "ADC Group A, channel 6 analog input (op-amp channel)."+ },+ {+ "number": "24",+ "name": "ADCINA7",+ "type": "input",+ "description": "ADC Group A, channel 7 analog input."+ },+ {+ "number": "25",+ "name": "ADCINB3",+ "type": "input",+ "description": "ADC Group B, channel 3 analog input."+ },+ {+ "number": "26",+ "name": "ADCINB4",+ "type": "input",+ "description": "ADC Group B, channel 4 analog input (op-amp channel, associated with M2GND)."+ },+ {+ "number": "27",+ "name": "M2GND",+ "type": "power_in",+ "description": "Ground pin for amplifier channels A6, B4 and B6."+ },+ {+ "number": "28",+ "name": "ADCINB5",+ "type": "input",+ "description": "ADC Group B, channel 5 analog input."+ },+ {+ "number": "29",+ "name": "ADCINB6",+ "type": "input",+ "description": "ADC Group B, channel 6 analog input (op-amp channel)."+ },+ {+ "number": "30",+ "name": "ADCINB0",+ "type": "input",+ "description": "ADC Group B, channel 0 analog input."+ },+ {+ "number": "31",+ "name": "ADCINB7",+ "type": "input",+ "description": "ADC Group B, channel 7 analog input (op-amp channel, associated with PFCGND)."+ },+ {+ "number": "32",+ "name": "PFCGND",+ "type": "power_in",+ "description": "Ground pin for amplifier channel B7."+ },+ {+ "number": "33",+ "name": "GPIO27",+ "type": "bidirectional",+ "description": "General-purpose I/O 27 with alternate SCITXDC (output)."+ },+ {+ "number": "34",+ "name": "GPIO31",+ "type": "bidirectional",+ "description": "General-purpose I/O 31 with internal pullup enabled by default; alternates CANTXA, SCITXDB and EPWM7B (outputs)."+ },+ {+ "number": "35",+ "name": "GPIO30",+ "type": "bidirectional",+ "description": "General-purpose I/O 30 with internal pullup enabled by default; alternates CANRXA (input), SCIRXDB (input) and EPWM7A (output)."+ },+ {+ "number": "36",+ "name": "GPIO9",+ "type": "bidirectional",+ "description": "General-purpose I/O 9 with alternates EPWM5B (output) and SCITXDB (output)."+ },+ {+ "number": "37",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin."+ },+ {+ "number": "38",+ "name": "VDDIO",+ "type": "power_in",+ "description": "Digital I/O buffer and flash memory power pin; single supply source when VREG is enabled; place a decoupling capacitor on each VDDIO pin."+ },+ {+ "number": "39",+ "name": "TEST2",+ "type": "bidirectional",+ "description": "Test pin reserved for TI; must be left unconnected."+ },+ {+ "number": "40",+ "name": "GPIO26",+ "type": "bidirectional",+ "description": "General-purpose I/O 26 with alternate SCIRXDC (input)."+ },+ {+ "number": "41",+ "name": "GPIO29",+ "type": "bidirectional",+ "description": "General-purpose I/O 29 with alternates SCITXDA (output), SCLA (I2C clock, open-drain), TZ3 (input) and CTRIPPFCOUT (output)."+ },+ {+ "number": "42",+ "name": "GPIO28",+ "type": "bidirectional",+ "description": "General-purpose I/O 28 with alternates SCIRXDA (input), SDAA (I2C data, open-drain) and TZ2 (input)."+ },+ {+ "number": "43",+ "name": "GPIO18",+ "type": "bidirectional",+ "description": "General-purpose I/O 18 with alternates SPICLKA (I/O), SCITXDB (output) and XCLKOUT; XCLKOUT is SYSCLKOUT divided by 1, 2 or 4, resets to SYSCLKOUT/4 and can be turned off by setting XCLKOUTDIV to 3."+ },+ {+ "number": "44",+ "name": "GPIO17",+ "type": "bidirectional",+ "description": "General-purpose I/O 17 with alternates SPISOMIA (I/O), EQEP1I (I/O), TZ3 (input) and CTRIPPFCOUT (output)."+ },+ {+ "number": "45",+ "name": "GPIO8",+ "type": "bidirectional",+ "description": "General-purpose I/O 8 with alternates EPWM5A (output) and ADCSOCAO (output)."+ },+ {+ "number": "46",+ "name": "GPIO25",+ "type": "bidirectional",+ "description": "General-purpose I/O 25; all alternate functions are reserved for this pin."+ },+ {+ "number": "47",+ "name": "GPIO16",+ "type": "bidirectional",+ "description": "General-purpose I/O 16 with alternates SPISIMOA (I/O), EQEP1S (I/O) and TZ2 (input)."+ },+ {+ "number": "48",+ "name": "GPIO12",+ "type": "bidirectional",+ "description": "General-purpose I/O 12 with alternates TZ1 (input), CTRIPM1OUT (output) and SCITXDA (output)."+ },+ {+ "number": "49",+ "name": "GPIO7",+ "type": "bidirectional",+ "description": "General-purpose I/O 7 with alternates EPWM4B (output) and SCIRXDA (input)."+ },+ {+ "number": "50",+ "name": "GPIO6",+ "type": "bidirectional",+ "description": "General-purpose I/O 6 with alternates EPWM4A (output), EPWMSYNCI (input) and EPWMSYNCO (output)."+ },+ {+ "number": "51",+ "name": "X2",+ "type": "output",+ "description": "On-chip crystal oscillator output; a quartz crystal or ceramic resonator is connected across X1 and X2, and X2 must be left unconnected if not used."+ },+ {+ "number": "52",+ "name": "X1",+ "type": "input",+ "description": "On-chip 1.8-V crystal oscillator input; a crystal or resonator is connected across X1 and X2, and the pin must be tied to GND if not used."+ },+ {+ "number": "53",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin."+ },+ {+ "number": "54",+ "name": "VDD",+ "type": "power_in",+ "description": "CPU and logic digital power pin; when the internal VREG is used, place one 1.2-µF capacitor between each VDD pin and ground (higher values allowed)."+ },+ {+ "number": "55",+ "name": "GPIO19",+ "type": "bidirectional",+ "description": "General-purpose I/O 19 with alternates XCLKIN (external oscillator input), SPISTEA (I/O), SCIRXDB (input) and ECAP1 (I/O); may glitch during power-up when the on-chip VREG is used."+ },+ {+ "number": "56",+ "name": "GPIO39",+ "type": "bidirectional",+ "description": "General-purpose I/O 39 with alternates SCIRXDC (input) and CTRIPPFCOUT (output)."+ },+ {+ "number": "57",+ "name": "GPIO38",+ "type": "bidirectional",+ "description": "General-purpose I/O 38 (default XCLKIN selection) with alternates TCK (JTAG clock, internal pullup) and XCLKIN (external oscillator input); avoid enabling the XCLKIN path during JTAG debug to prevent contention with TCK, and may glitch during power-up when VREG is used."+ },+ {+ "number": "58",+ "name": "GPIO37",+ "type": "tri_state",+ "description": "JTAG scan out (TDO) with 8 mA drive, shifted out on the falling edge of TCK; also GPIO37, and may glitch during power-up when VREG is used."+ },+ {+ "number": "59",+ "name": "GPIO35",+ "type": "bidirectional",+ "description": "JTAG test data input (TDI) with internal pullup, clocked into the selected register on the rising edge of TCK; also GPIO35 and may glitch during power-up when VREG is used."+ },+ {+ "number": "60",+ "name": "GPIO36",+ "type": "bidirectional",+ "description": "JTAG test-mode select (TMS) with internal pullup, clocked into the TAP controller on the rising edge of TCK; also GPIO36 and may glitch during power-up when VREG is used."+ },+ {+ "number": "61",+ "name": "GPIO11",+ "type": "bidirectional",+ "description": "General-purpose I/O 11 with alternates EPWM6B (output) and SCIRXDB (input)."+ },+ {+ "number": "62",+ "name": "GPIO5",+ "type": "bidirectional",+ "description": "General-purpose I/O 5 with alternates EPWM3B (output), SPISIMOA (I/O) and ECAP1 (I/O)."+ },+ {+ "number": "63",+ "name": "GPIO4",+ "type": "bidirectional",+ "description": "General-purpose I/O 4 with alternate EPWM3A (output)."+ },+ {+ "number": "64",+ "name": "GPIO40",+ "type": "bidirectional",+ "description": "General-purpose I/O 40 with internal pullup enabled by default; alternate EPWM7A (output)."+ },+ {+ "number": "65",+ "name": "GPIO10",+ "type": "bidirectional",+ "description": "General-purpose I/O 10 with alternates EPWM6A (output) and ADCSOCBO (output)."+ },+ {+ "number": "66",+ "name": "GPIO3",+ "type": "bidirectional",+ "description": "General-purpose I/O 3 with alternates EPWM2B (output) and SPISOMIA (I/O)."+ },+ {+ "number": "67",+ "name": "GPIO2",+ "type": "bidirectional",+ "description": "General-purpose I/O 2 with alternate EPWM2A (output)."+ },+ {+ "number": "68",+ "name": "GPIO1",+ "type": "bidirectional",+ "description": "General-purpose I/O 1 with alternates EPWM1B (output) and CTRIPM1OUT (output)."+ },+ {+ "number": "69",+ "name": "GPIO0",+ "type": "bidirectional",+ "description": "General-purpose I/O 0 with alternate EPWM1A (output); PWM-pin pullup is not enabled at reset."+ },+ {+ "number": "70",+ "name": "VDDIO",+ "type": "power_in",+ "description": "Digital I/O buffer and flash memory power pin; single supply source when VREG is enabled; place a decoupling capacitor on each VDDIO pin."+ },+ {+ "number": "71",+ "name": "VREGENZ",+ "type": "input",+ "description": "Internal voltage regulator enable with internal pulldown; tie to VSS to enable the internal 1.8-V VREG, or tie to VDDIO to disable it and use an external 1.8-V supply."+ },+ {+ "number": "72",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin."+ },+ {+ "number": "73",+ "name": "VDD",+ "type": "power_in",+ "description": "CPU and logic digital power pin; when the internal VREG is used, place one 1.2-µF capacitor between each VDD pin and ground (higher values allowed)."+ },+ {+ "number": "74",+ "name": "GPIO34",+ "type": "bidirectional",+ "description": "General-purpose I/O 34 with alternate CTRIPPFCOUT (output); not glitch-free and may glitch during power-up when the on-chip VREG is used."+ },+ {+ "number": "75",+ "name": "GPIO15",+ "type": "bidirectional",+ "description": "General-purpose I/O 15 with alternates TZ1 (input), CTRIPM1OUT (output) and SCIRXDB (input)."+ },+ {+ "number": "76",+ "name": "GPIO13",+ "type": "bidirectional",+ "description": "General-purpose I/O 13 with alternate TZ2 (input, trip zone)."+ },+ {+ "number": "77",+ "name": "GPIO14",+ "type": "bidirectional",+ "description": "General-purpose I/O 14 with alternates TZ3 (input), CTRIPPFCOUT (output) and SCITXDB (output)."+ },+ {+ "number": "78",+ "name": "GPIO20",+ "type": "bidirectional",+ "description": "General-purpose I/O 20 with internal pullup enabled by default; alternates EQEP1A (input), EPWM7A (output) and CTRIPM1OUT (output)."+ },+ {+ "number": "79",+ "name": "GPIO21",+ "type": "bidirectional",+ "description": "General-purpose I/O 21 with internal pullup enabled by default; alternates EQEP1B (input) and EPWM7B (output)."+ },+ {+ "number": "80",+ "name": "GPIO23",+ "type": "bidirectional",+ "description": "General-purpose I/O 23 with alternates EQEP1I (I/O) and SCIRXDB (input)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Package and variant check: TMS320F28053PNS is the 80-pin PN LQFP with the S suffix (-40 to 125 °C). ; Source is a Chinese translation of SPRS797. Pin numbers and types come from the signal description t; Pin 18 is printed as ADCINA0/VREFOUT, but the table types it as input even though VREFOUT is an outp"+ ],+ "pages_sent": 30,+ "cost_usd": 0.2399,+ "at": "2026-10-08T04:46:34"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tms320f28054f",+ "pages": 159,+ "sha256": "aaaaedb6c548633c",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 80,+ "described": 80,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tms320f28053pns.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 14,+ 14,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f782bdbc6327d920be33e2b9906695d7c3690117933775c3f145eac71f2013ac",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tms320f28053pns-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 14,+ 14,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "3d57afcbe329c6cf4ac529945c80b11bef1d3b986dc87173e88fb9663e69db8d",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}