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TMS320F28035PNS

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TMS320F28035PNS

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)

TMS320F28035PNS from Texas Instruments, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO22/EQEP1S/LINTXA bidirectional General-purpose I/O 22 (default), alternate eQEP1 strobe or LIN transmit A; internal pull-up selectable.
2 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO bidirectional General-purpose I/O 32 (default), alternate I2C data (open-drain), ePWM sync input or ADC start-of-conversion A output.
3 GPIO33/SCLA/EPWMSYNCO/ADCSOCBO bidirectional General-purpose I/O 33 (default), alternate I2C clock (open-drain), ePWM sync output or ADC start-of-conversion B output.
4 GPIO23/EQEP1I/LINRXA bidirectional General-purpose I/O 23 (default), alternate eQEP1 index or LIN receive A.
5 GPIO42/COMP1OUT bidirectional General-purpose I/O 42 (default) or direct output of comparator 1.
6 GPIO43/COMP2OUT bidirectional General-purpose I/O 43 (default) or direct output of comparator 2.
7 VDD power_in CPU and logic digital power pin; with internal VREG place a 1.2 µF capacitor between each VDD pin and ground.
8 VSS power_in Digital ground pin.
9 XRS bidirectional Device reset input and watchdog reset output (open-drain with internal pull-up); use a 2.2 kΩ to 10 kΩ resistor to VDDIO and no more than 100 nF to VSS.
10 TRST input JTAG test reset with internal pull-down; active high, must be held low during normal operation, external pull-down resistor required (typically 2.2 kΩ).
11 ADCINA7 input ADC group A, channel 7 input.
12 ADCINA6/COMP3A/AIO6 bidirectional ADC group A channel 6 input, comparator 3A input or digital AIO6.
13 ADCINA5 input ADC group A, channel 5 input.
14 ADCINA4/COMP2A/AIO4 bidirectional ADC group A channel 4 input, comparator 2A input or digital AIO4.
15 ADCINA3 input ADC group A, channel 3 input.
16 ADCINA2/COMP1A/AIO2 bidirectional ADC group A channel 2 input, comparator 1A input or digital AIO2.
17 ADCINA1 input ADC group A, channel 1 input.
18 ADCINA0 input ADC group A, channel 0 input.
19 VREFHI input ADC external reference high, used only in ADC external reference mode; must not exceed VDDA.
20 VDDA power_in Analog power pin; connect a 2.2 µF (typical) capacitor near this pin; 2.97 V to 3.63 V recommended.
21 VSSA power_in Analog ground pin.
22 VREFLO input ADC external reference low.
23 ADCINB0 input ADC group B, channel 0 input.
24 ADCINB1 input ADC group B, channel 1 input.
25 ADCINB2/COMP1B/AIO10 bidirectional ADC group B channel 2 input, comparator 1B input or digital AIO10.
26 ADCINB3 input ADC group B, channel 3 input.
27 ADCINB4/COMP2B/AIO12 bidirectional ADC group B channel 4 input, comparator 2B input or digital AIO12.
28 ADCINB5 input ADC group B, channel 5 input.
29 ADCINB6/COMP3B/AIO14 bidirectional ADC group B channel 6 input, comparator 3B input or digital AIO14.
30 ADCINB7 input ADC group B, channel 7 input.
31 GPIO27/HRCAP2/SPISTEB bidirectional General-purpose I/O 27 (default), alternate HRCAP2 input or SPI-B slave transmit enable.
32 GPIO31/CANTXA bidirectional General-purpose I/O 31 (default) or CAN transmit.
33 GPIO30/CANRXA bidirectional General-purpose I/O 30 (default) or CAN receive.
34 GPIO29/SCITXDA/SCLA/TZ3 bidirectional General-purpose I/O 29 (default), alternate SCI transmit, I2C clock (open-drain) or trip zone 3 input.
35 VSS power_in Digital ground pin.
36 VDDIO power_in Digital I/O buffer and Flash power pin; single supply when VREG enabled, 2.97 V to 3.63 V, decouple each pin.
37 GPIO26/HRCAP1/SPICLKB bidirectional General-purpose I/O 26 (default), alternate HRCAP1 input or SPI-B clock.
38 TEST2 bidirectional Test pin reserved for TI; must be left unconnected.
39 GPIO9/EPWM5B/LINTXA/HRCAP1 bidirectional General-purpose I/O 9 (default), alternate ePWM5 output B, LIN transmit A or HRCAP1 input.
40 GPIO28/SCIRXDA/SDAA/TZ2 bidirectional General-purpose I/O 28 (default), alternate SCI receive, I2C data (open-drain) or trip zone 2 input.
41 GPIO18/SPICLKA/LINTXA/XCLKOUT bidirectional General-purpose I/O 18 (default), alternate SPI-A clock, LIN transmit or XCLKOUT output clock.
42 GPIO17/SPISOMIA/TZ3 bidirectional General-purpose I/O 17 (default), alternate SPI-A slave out/master in or trip zone 3 input.
43 GPIO8/EPWM5A/ADCSOCAO bidirectional General-purpose I/O 8 (default), alternate ePWM5 output A or ADC start-of-conversion A output.
44 GPIO25/SPISOMIB bidirectional General-purpose I/O 25 (default) or SPI-B slave out/master in.
45 GPIO44 bidirectional General-purpose I/O 44.
46 GPIO16/SPISIMOA/TZ2 bidirectional General-purpose I/O 16 (default), alternate SPI-A slave in/master out or trip zone 2 input.
47 GPIO12/TZ1/SCITXDA/SPISIMOB bidirectional General-purpose I/O 12 (default), alternate trip zone 1 input, SCI transmit or SPI-B slave in/master out.
48 GPIO41/EPWM7B bidirectional General-purpose I/O 41 (default) or ePWM7 output B.
49 GPIO7/EPWM4B/SCIRXDA bidirectional General-purpose I/O 7 (default), alternate ePWM4 output B or SCI receive.
50 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO bidirectional General-purpose I/O 6 (default), alternate ePWM4 output A, external ePWM sync input or output.
51 X2 output On-chip 1.8 V crystal oscillator output; connect crystal/resonator between X1 and X2, leave unconnected if unused.
52 X1 input 1.8 V on-chip crystal oscillator input; connect to GND if unused, never apply 3.3 V.
53 VSS power_in Digital ground pin.
54 VDD power_in CPU and logic digital power pin; with internal VREG place a 1.2 µF capacitor between each VDD pin and ground.
55 GPIO19/XCLKIN/SPISTEA/LINRXA/ECAP1 bidirectional General-purpose I/O 19 (default), alternate external oscillator input, SPI-A slave transmit enable, LIN receive or eCAP1.
56 GPIO39 bidirectional General-purpose I/O 39.
57 GPIO38/TCK/XCLKIN bidirectional General-purpose I/O 38 (default), JTAG test clock input with internal pull-up, or external oscillator input.
58 GPIO37/TDO bidirectional General-purpose I/O 37 (default) or JTAG test data output (8 mA drive); also boot-mode select pin.
59 GPIO35/TDI bidirectional General-purpose I/O 35 (default) or JTAG test data input with internal pull-up.
60 GPIO36/TMS bidirectional General-purpose I/O 36 (default) or JTAG test mode select with internal pull-up.
61 GPIO11/EPWM6B/LINRXA/HRCAP2 bidirectional General-purpose I/O 11 (default), alternate ePWM6 output B, LIN receive or HRCAP2 input.
62 GPIO5/EPWM3B/SPISIMOA/ECAP1 bidirectional General-purpose I/O 5 (default), alternate ePWM3 output B, SPI-A slave in/master out or eCAP1.
63 GPIO4/EPWM3A bidirectional General-purpose I/O 4 (default) or ePWM3 output A with HRPWM channel.
64 GPIO40/EPWM7A bidirectional General-purpose I/O 40 (default) or ePWM7 output A with HRPWM channel.
65 GPIO10/EPWM6A/ADCSOCBO bidirectional General-purpose I/O 10 (default), alternate ePWM6 output A or ADC start-of-conversion B output.
66 GPIO3/EPWM2B/SPISOMIA/COMP2OUT bidirectional General-purpose I/O 3 (default), alternate ePWM2 output B, SPI-A slave out/master in or comparator 2 output.
67 GPIO2/EPWM2A bidirectional General-purpose I/O 2 (default) or ePWM2 output A with HRPWM channel.
68 GPIO1/EPWM1B/COMP1OUT bidirectional General-purpose I/O 1 (default), alternate ePWM1 output B or comparator 1 direct output.
69 GPIO0/EPWM1A bidirectional General-purpose I/O 0 (default) or ePWM1 output A with HRPWM channel.
70 VDDIO power_in Digital I/O buffer and Flash power pin; single supply when VREG enabled, 2.97 V to 3.63 V, decouple each pin.
71 VSS power_in Digital ground pin.
72 VDD power_in CPU and logic digital power pin; with internal VREG place a 1.2 µF capacitor between each VDD pin and ground.
73 VREGENZ input Internal VREG enable with internal pull-down; tie to VSS to enable the internal 1.8 V VREG, to VDDIO to disable it and use external 1.8 V.
74 GPIO34/COMP2OUT/COMP3OUT bidirectional General-purpose I/O 34 (default), comparator 2 or 3 direct output; boot-mode select pin.
75 GPIO15/TZ1/LINRXA/SPISTEB bidirectional General-purpose I/O 15 (default), alternate trip zone 1 input, LIN receive or SPI-B slave transmit enable.
76 GPIO13/TZ2/SPISOMIB bidirectional General-purpose I/O 13 (default), alternate trip zone 2 input or SPI-B slave out/master in.
77 GPIO14/TZ3/LINTXA/SPICLKB bidirectional General-purpose I/O 14 (default), alternate trip zone 3 input, LIN transmit or SPI-B clock.
78 GPIO20/EQEP1A/COMP1OUT bidirectional General-purpose I/O 20 (default), alternate eQEP1 input A or comparator 1 direct output.
79 GPIO21/EQEP1B/COMP2OUT bidirectional General-purpose I/O 21 (default), alternate eQEP1 input B or comparator 2 direct output.
80 GPIO24/ECAP1/SPISIMOB bidirectional General-purpose I/O 24 (default), alternate eCAP1 or SPI-B slave in/master out.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-80(12x12)
Category Embedded Processors & Controllers
Pins 80

CAD (KiCad official)

  • Symbol: TMS320F28035PNS
  • Footprint: Package_QFP:LQFP-80_12x12mm_P0.5mm
  • 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)
  • 3D model files: tms320f28035pns-etched.step / tms320f28035pns-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f28035pns.step / tms320f28035pns.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (176 pp, sha256 cb9ccecfd6b5c484, retrieved 2026-10-05, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF