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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

TMS320F28034RSHT

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-56-EP(7x7)

TMS320F28034RSHT from Texas Instruments, in a VQFN-56-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GPIO22/EQEP1S/LINTXA	bidirectional	General-purpose I/O 22 with internal pull-up enabled after reset, alternating to EQEP1 strobe (I/O) and LIN transmit (output); inputs are not 5 V tolerant.
2	GPIO23/EQEP1I/LINRXA	bidirectional	General-purpose I/O 23 with internal pull-up enabled after reset, alternating to EQEP1 index (I/O) and LIN receive (input); inputs are not 5 V tolerant.
3	VDD	power_in	CPU and logic digital supply; with the internal VREG enabled place at least 1.2 µF from each VDD pin to ground, or supply 1.71-1.995 V externally when VREG is disabled.
4	VSS	power_in	Digital ground pin.
5	XRS	bidirectional	Device reset input and watchdog reset output (open-drain with internal pull-up), driven low during POR/BOR and for 512 OSCCLK cycles on a watchdog reset; use a 2.2 kΩ to 10 kΩ resistor from XRS to VDDIO and a capacitor of 100 nF or less to VSS if filtering is required.
6	TRST	input	JTAG test reset with internal pull-down; it must be held low during normal operation and an external pull-up (about 2.2 kΩ typical) is required on this pin.
7	ADCINA7	input	ADC group A channel 7 analog input.
8	ADCINA6/COMP3A/AIO6	input	ADC group A channel 6 analog input, also comparator 3A input and digital AIO6; an unused ADC input that is shared with AIO should be connected to ground through a 1 kΩ resistor, not directly.
9	ADCINA4/COMP2A/AIO4	input	ADC group A channel 4 analog input, also comparator 2A input and digital AIO4; unused shared inputs should go to ground through 1 kΩ.
10	ADCINA3	input	ADC group A channel 3 analog input, 0 V to 3.3 V full scale with the internal reference.
11	ADCINA2/COMP1A/AIO2	input	ADC group A channel 2 analog input, also comparator 1A input and digital AIO2; unused shared inputs should go to ground through 1 kΩ.
12	ADCINA1	input	ADC group A channel 1 analog input.
13	ADCINA0/VREFHI	input	ADC group A channel 0 analog input, shared with the external ADC reference VREFHI (external reference mode only); it cannot be used as both at the same time, and VREFHI must not exceed VDDA.
14	VDDA	power_in	Analog supply, 2.97 V to 3.63 V (3.3 V nominal); place a 2.2 µF (typical) capacitor near this pin.
15	VSSA/VREFLO	power_in	Analog ground; the ADC low reference VREFLO is always connected to VSSA on the 56-pin RSH device.
16	ADCINB1	input	ADC group B channel 1 analog input.
17	ADCINB2/COMP1B/AIO10	input	ADC group B channel 2 analog input, also comparator 1B input and digital AIO10; unused shared inputs should go to ground through 1 kΩ.
18	ADCINB3	input	ADC group B channel 3 analog input.
19	ADCINB4/COMP2B/AIO12	input	ADC group B channel 4 analog input, also comparator 2B input and digital AIO12; unused shared inputs should go to ground through 1 kΩ.
20	ADCINB6/COMP3B/AIO14	input	ADC group B channel 6 analog input, also comparator 3B input and digital AIO14; unused shared inputs should go to ground through 1 kΩ.
21	ADCINB7	input	ADC group B channel 7 analog input.
22	GPIO31/CANTXA	bidirectional	General-purpose I/O 31 with internal pull-up enabled after reset, alternating to eCAN transmit (CANTXA, output).
23	GPIO30/CANRXA	bidirectional	General-purpose I/O 30 with internal pull-up enabled after reset, alternating to eCAN receive (CANRXA, input).
24	GPIO29/SCITXDA/SCLA/TZ3	bidirectional	General-purpose I/O 29 alternating to SCI-A transmit (output), I2C-A clock (open-drain I/O) and trip-zone input TZ3.
25	VSS	power_in	Digital ground pin.
26	VDDIO	power_in	Digital I/O buffer and flash supply, 2.97 V to 3.63 V (3.3 V nominal); place a decoupling capacitor on each VDDIO pin.
27	TEST2	unconnected	Reserved for TI; must be left unconnected on the application board.
28	GPIO28/SCIRXDA/SDAA/TZ2	bidirectional	General-purpose I/O 28 alternating to SCI-A receive (input), I2C-A data (open-drain I/O) and trip-zone input TZ2.
29	GPIO18/SPICLKA/LINTXA/XCLKOUT	bidirectional	General-purpose I/O 18 alternating to SPI-A clock, LIN transmit and XCLKOUT output (SYSCLKOUT/4 at reset, controlled by XCLKOUTDIV).
30	GPIO17/SPISOMIA/TZ3	bidirectional	General-purpose I/O 17 alternating to SPI-A slave output/master input and trip-zone input TZ3.
31	GPIO16/SPISIMOA/TZ2	bidirectional	General-purpose I/O 16 alternating to SPI-A slave input/master output and trip-zone input TZ2.
32	GPIO12/TZ1/SCITXDA	bidirectional	General-purpose I/O 12 alternating to trip-zone input TZ1 and SCI-A transmit (output).
33	GPIO7/EPWM4B/SCIRXDA	bidirectional	General-purpose I/O 7 alternating to ePWM4B output and SCI-A receive (input).
34	GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO	bidirectional	General-purpose I/O 6 alternating to ePWM4A output (with HRPWM), external ePWM sync input and sync output.
35	X2	output	On-chip crystal oscillator output; a crystal or ceramic resonator must be connected between X1 and X2, and X2 must be left unconnected if not used.
36	X1	input	1.8 V on-chip crystal oscillator input that must not be driven with 3.3 V levels; it must be connected to GND if not used.
37	VSS	power_in	Digital ground pin.
38	VDD	power_in	CPU and logic digital supply; with the internal VREG enabled place at least 1.2 µF from each VDD pin to ground.
39	GPIO19/XCLKIN/SPISTEA/LINRXA/ECAP1	bidirectional	General-purpose I/O 19 that also serves as the external oscillator/clock input XCLKIN (3.3 V), alternating to SPI-A slave transmit enable, LIN receive and eCAP1; it can show a power-on glitch when the internal VREG is used.
40	GPIO38/TCK/XCLKIN	bidirectional	General-purpose I/O 38 that is also the JTAG test clock TCK (internal pull-up) and an alternate XCLKIN input; if used for an external clock, an alternate clock source is needed during JTAG debug.
41	GPIO37/TDO	tri_state	JTAG scan data output TDO (8 mA drive), shifted out on the TCK falling edge; the pin is also GPIO37 and can show a power-on glitch when the internal VREG is used.
42	GPIO35/TDI	bidirectional	General-purpose I/O 35 that is also the JTAG test data input TDI with internal pull-up, clocked on the TCK rising edge; it can show a power-on glitch when the internal VREG is used.
43	GPIO36/TMS	bidirectional	General-purpose I/O 36 that is also the JTAG test mode select TMS with internal pull-up, clocked on the TCK rising edge; it can show a power-on glitch when the internal VREG is used.
44	GPIO5/EPWM3B/SPISIMOA/ECAP1	bidirectional	General-purpose I/O 5 alternating to ePWM3B output, SPI-A slave input/master output and eCAP1 I/O.
45	GPIO4/EPWM3A	bidirectional	General-purpose I/O 4 alternating to ePWM3A output (with HRPWM).
46	GPIO3/EPWM2B/SPISOMIA/COMP2OUT	bidirectional	General-purpose I/O 3 alternating to ePWM2B output, SPI-A slave output/master input and comparator 2 direct output.
47	GPIO2/EPWM2A	bidirectional	General-purpose I/O 2 alternating to ePWM2A output (with HRPWM).
48	GPIO1/EPWM1B/COMP1OUT	bidirectional	General-purpose I/O 1 alternating to ePWM1B output and comparator 1 direct output.
49	GPIO0/EPWM1A	bidirectional	General-purpose I/O 0 alternating to ePWM1A output (with HRPWM).
50	VDDIO	power_in	Digital I/O buffer and flash supply, 2.97 V to 3.63 V (3.3 V nominal); place a decoupling capacitor on each VDDIO pin.
51	VSS	power_in	Digital ground pin.
52	VDD	power_in	CPU and logic digital supply; with the internal VREG enabled place at least 1.2 µF from each VDD pin to ground.
53	VREGENZ	input	Internal regulator enable with internal pull-down: connect to VSS to enable the internal 1.8 V VREG, or to VDDIO to disable it and use an external 1.8 V VDD supply.
54	GPIO34/COMP2OUT/COMP3OUT	bidirectional	General-purpose I/O 34 alternating to comparator 2 and comparator 3 direct outputs; it can show a power-on glitch when the internal VREG is used.
55	GPIO20/EQEP1A/COMP1OUT	bidirectional	General-purpose I/O 20 alternating to EQEP1 input A and comparator 1 direct output.
56	GPIO21/EQEP1B/COMP2OUT	bidirectional	General-purpose I/O 21 alternating to EQEP1 input B and comparator 2 direct output.
57	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-56-EP(7x7)
Category	Embedded Processors & Controllers
Pins	57

CAD (KiCad official)

Symbol: TMS320F28034RSHT
Footprint: Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP4x4mm
3D model: VQFN-56-EP(7x7) (KiCad packages3D, STEP)
3D model files: tms320f28034rsht-etched.step / tms320f28034rsht-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f28034rsht.step / tms320f28034rsht.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (176 pp, sha256 cb9ccecfd6b5c484, retrieved 2026-10-11, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF