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TMS320F28034RSHS

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Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-56-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TMS320F28034RSHS

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-56-EP(7x7)

TMS320F28034RSHS from Texas Instruments, in a VQFN-56-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO22/EQEP1S/LINTXA bidirectional GPIO22 (I/O/Z, default at reset) with eQEP1 strobe or LIN transmit A alternate functions.
2 GPIO23/EQEP1I/LINRXA bidirectional GPIO23 (I/O/Z, default at reset) with eQEP1 index or LIN receive A alternate functions.
3 VDD power_in CPU and logic digital supply; with the internal VREG place a 1.2uF capacitor from each VDD pin to ground.
4 VSS power_in Digital ground.
5 XRS bidirectional Device reset input and watchdog reset output (open-drain with internal pullup, driven low by POR/BOR); use a 2.2k-10k resistor to VDDIO and at most 100nF to VSS.
6 TRST input JTAG test reset with internal pulldown; active high, must be held low in normal operation and needs an external pulldown per the datasheet (typically 2.2k).
7 ADCINA7 input ADC group A channel 7 input.
8 ADCINA6/COMP3A/AIO6 bidirectional ADC group A channel 6 input, comparator 3A input, or digital AIO6.
9 ADCINA4/COMP2A/AIO4 bidirectional ADC group A channel 4 input, comparator 2A input, or digital AIO4.
10 ADCINA3 input ADC group A channel 3 input.
11 ADCINA2/COMP1A/AIO2 bidirectional ADC group A channel 2 input, comparator 1A input, or digital AIO2.
12 ADCINA1 input ADC group A channel 1 input.
13 ADCINA0/VREFHI input ADC group A channel 0 input or external reference high (VREFHI); the two share this pin and cannot be used simultaneously, and VREFHI must not exceed VDDA.
14 VDDA power_in Analog supply; connect a 2.2uF (typical) capacitor near this pin; recommended 2.97V to 3.63V.
15 VSSA/VREFLO power_in Analog ground; VREFLO is always connected to VSSA on the RSH package.
16 ADCINB1 input ADC group B channel 1 input.
17 ADCINB2/COMP1B/AIO10 bidirectional ADC group B channel 2 input, comparator 1B input, or digital AIO10.
18 ADCINB3 input ADC group B channel 3 input.
19 ADCINB4/COMP2B/AIO12 bidirectional ADC group B channel 4 input, comparator 2B input, or digital AIO12.
20 ADCINB6/COMP3B/AIO14 bidirectional ADC group B channel 6 input, comparator 3B input, or digital AIO14.
21 ADCINB7 input ADC group B channel 7 input.
22 GPIO31/CANTXA bidirectional GPIO31 (I/O/Z, default at reset) with CAN transmit alternate function.
23 GPIO30/CANRXA bidirectional GPIO30 (I/O/Z, default at reset) with CAN receive alternate function.
24 GPIO29/SCITXDA/SCLA/TZ3 bidirectional GPIO29 (I/O/Z, default at reset) with SCI transmit, I2C clock (open-drain) or trip zone 3 alternates; 8mA group 2 pin.
25 VSS power_in Digital ground.
26 VDDIO power_in Digital I/O buffer and flash supply; recommended 2.97V to 3.63V; place a decoupling capacitor on each pin.
27 TEST2 unconnected Test pin reserved for TI; must be left unconnected.
28 GPIO28/SCIRXDA/SDAA/TZ2 bidirectional GPIO28 (I/O/Z, default at reset) with SCI receive, I2C data (open-drain) or trip zone 2 alternates; 8mA group 2 pin.
29 GPIO18/SPICLKA/LINTXA/XCLKOUT bidirectional GPIO18 (I/O/Z, default at reset) with SPI-A clock, LIN transmit or XCLKOUT (SYSCLKOUT, /2 or /4) alternates.
30 GPIO17/SPISOMIA/TZ3 bidirectional GPIO17 (I/O/Z, default at reset) with SPI-A SOMI or trip zone 3 alternates.
31 GPIO16/SPISIMOA/TZ2 bidirectional GPIO16 (I/O/Z, default at reset) with SPI-A SIMO or trip zone 2 alternates.
32 GPIO12/TZ1/SCITXDA bidirectional GPIO12 (I/O/Z, default at reset) with trip zone 1 or SCI transmit alternates (SPI-B function is PN only).
33 GPIO7/EPWM4B/SCIRXDA bidirectional GPIO7 (I/O/Z, default at reset) with ePWM4 output B or SCI receive alternates.
34 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO bidirectional GPIO6 (I/O/Z, default at reset) with ePWM4 output A/HRPWM, external sync in or sync out alternates.
35 X2 output On-chip crystal oscillator output; connect crystal/resonator between X1 and X2, leave unconnected if unused.
36 X1 input 1.8V on-chip crystal oscillator input; connect to GND if unused, never apply 3.3V levels.
37 VSS power_in Digital ground.
38 VDD power_in CPU and logic digital supply; with the internal VREG place a 1.2uF capacitor from each VDD pin to ground.
39 GPIO19/XCLKIN/SPISTEA/LINRXA/ECAP1 bidirectional GPIO19 (I/O/Z, default at reset) with external oscillator input path, SPI-A STE, LIN receive or eCAP1 alternates; glitches during power-up with on-chip VREG.
40 GPIO38/TCK/XCLKIN bidirectional GPIO38 (I/O/Z) used as JTAG TCK input with internal pullup, or external oscillator input (default XCLKIN source).
41 GPIO37/TDO bidirectional GPIO37 (I/O/Z) used as JTAG TDO scan output (8mA drive); also boot mode select pin.
42 GPIO35/TDI bidirectional GPIO35 (I/O/Z) used as JTAG TDI input with internal pullup.
43 GPIO36/TMS bidirectional GPIO36 (I/O/Z) used as JTAG TMS input with internal pullup.
44 GPIO5/EPWM3B/SPISIMOA/ECAP1 bidirectional GPIO5 (I/O/Z, default at reset) with ePWM3 output B, SPI-A SIMO or eCAP1 alternates.
45 GPIO4/EPWM3A bidirectional GPIO4 (I/O/Z, default at reset) with ePWM3 output A/HRPWM alternate.
46 GPIO3/EPWM2B/SPISOMIA/COMP2OUT bidirectional GPIO3 (I/O/Z, default at reset) with ePWM2 output B, SPI-A SOMI or comparator 2 output alternates.
47 GPIO2/EPWM2A bidirectional GPIO2 (I/O/Z, default at reset) with ePWM2 output A/HRPWM alternate.
48 GPIO1/EPWM1B/COMP1OUT bidirectional GPIO1 (I/O/Z, default at reset) with ePWM1 output B or comparator 1 output alternates.
49 GPIO0/EPWM1A bidirectional GPIO0 (I/O/Z, default at reset) with ePWM1 output A/HRPWM alternate.
50 VDDIO power_in Digital I/O buffer and flash supply; recommended 2.97V to 3.63V; place a decoupling capacitor on each pin.
51 VSS power_in Digital ground.
52 VDD power_in CPU and logic digital supply; with the internal VREG place a 1.2uF capacitor from each VDD pin to ground.
53 VREGENZ input Internal VREG enable with internal pulldown; tie to VSS to enable the 1.8V VREG or to VDDIO to disable it and use an external 1.8V supply.
54 GPIO34/COMP2OUT/COMP3OUT bidirectional GPIO34 (I/O/Z, default at reset) with comparator 2 or 3 output alternates; also boot mode select pin.
55 GPIO20/EQEP1A/COMP1OUT bidirectional GPIO20 (I/O/Z, default at reset) with eQEP1 input A or comparator 1 output alternates.
56 GPIO21/EQEP1B/COMP2OUT bidirectional GPIO21 (I/O/Z, default at reset) with eQEP1 input B or comparator 2 output alternates.
57 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-56-EP(7x7)
Category Embedded Processors & Controllers
Pins 57

CAD (KiCad official)

  • Symbol: TMS320F28034RSHS
  • Footprint: Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP4x4mm
  • 3D model: VQFN-56-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: tms320f28034rshs-etched.step / tms320f28034rshs-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f28034rshs.step / tms320f28034rshs.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (176 pp, sha256 cb9ccecfd6b5c484, retrieved 2026-10-06, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF