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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

TMS320F28034PNT

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)

TMS320F28034PNT from Texas Instruments, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GPIO22/EQEP1S/LINTXA	bidirectional	General-purpose I/O 22 (default, 3.3V I/O with optional weak pull-up), alternate function eQEP1 index/strobe input or LIN transmit data output.
2	GPIO32/SDAA/EPWMSYNCI/ADCSOCAO	bidirectional	General-purpose I/O 32, alternate function I2C SDA data line, ePWM external sync input, or ADC-A start-of-conversion output.
3	GPIO33/SCLA/EPWMSYNCO/ADCSOCBO	bidirectional	General-purpose I/O 33, alternate function I2C SCL clock line, ePWM sync output, or ADC-B start-of-conversion output.
4	GPIO23/EQEP1I/LINRXA	bidirectional	General-purpose I/O 23, alternate function eQEP1 index input or LIN receive data input.
5	GPIO42/COMP1OUT	bidirectional	General-purpose I/O 42, alternate function analog comparator 1 digital output.
6	GPIO43/COMP2OUT	bidirectional	General-purpose I/O 43, alternate function analog comparator 2 digital output.
7	VDD	power_in	Digital core logic supply input; internally regulated single-rail device sources this from the on-chip VREG unless bypassed.
8	VSS	power_in	Digital core/logic ground reference.
9	XRS	bidirectional	External reset pin; open-drain, active-low device reset that can be driven externally or driven low by the on-chip POR/BOR circuit.
10	TRST	input	JTAG test reset with internal pull-down; when driven high the scan system takes control of the device, and TI notes this pin is actually a high-level-active test pin that must be held low during normal functional operation with an external pull-down resistor (e.g. 2.2 kΩ).
11	ADCINA7	input	Analog input channel A7 to the 12-bit ADC sample-and-hold A, full-scale range 0V to 3.3V or ratiometric to VREFHI/VREFLO.
12	ADCINA6/COMP3A/AIO6	input	Analog input channel A6 to the ADC, alternate function comparator 3 A-side analog input or analog I/O 6.
13	ADCINA5	input	Analog input channel A5 to the 12-bit ADC sample-and-hold A.
14	ADCINA4/COMP2A/AIO4	input	Analog input channel A4 to the ADC, alternate function comparator 2 A-side analog input or analog I/O 4.
15	ADCINA3	input	Analog input channel A3 to the 12-bit ADC sample-and-hold A.
16	ADCINA2/COMP1A/AIO2	input	Analog input channel A2 to the ADC, alternate function comparator 1 A-side analog input or analog I/O 2.
17	ADCINA1	input	Analog input channel A1 to the 12-bit ADC sample-and-hold A.
18	ADCINA0	input	Analog input channel A0 to the 12-bit ADC sample-and-hold A.
19	VREFHI	power_in	External high ADC voltage reference input; when used, VREFHI must not exceed VDDA in either internal or external reference mode.
20	VDDA	power_in	3.3V analog supply for the ADC and comparator modules.
21	VSSA	power_in	Analog ground reference for the ADC and comparator modules.
22	VREFLO	power_in	External low ADC voltage reference input, tied to VSSA when the internal bandgap reference mode is used.
23	ADCINB0	input	Analog input channel B0 to the 12-bit ADC sample-and-hold B.
24	ADCINB1	input	Analog input channel B1 to the 12-bit ADC sample-and-hold B.
25	ADCINB2/COMP1B/AIO10	input	Analog input channel B2 to the ADC, alternate function comparator 1 B-side analog input or analog I/O 10.
26	ADCINB3	input	Analog input channel B3 to the 12-bit ADC sample-and-hold B.
27	ADCINB4/COMP2B/AIO12	input	Analog input channel B4 to the ADC, alternate function comparator 2 B-side analog input or analog I/O 12.
28	ADCINB5	input	Analog input channel B5 to the 12-bit ADC sample-and-hold B.
29	ADCINB6/COMP3B/AIO14	input	Analog input channel B6 to the ADC, alternate function comparator 3 B-side analog input or analog I/O 14.
30	ADCINB7	input	Analog input channel B7 to the 12-bit ADC sample-and-hold B.
31	GPIO27/HRCAP2/SPISTEB	bidirectional	General-purpose I/O 27, alternate function high-resolution capture input 2 or SPI-B slave transmit enable.
32	GPIO31/CANTXA	bidirectional	General-purpose I/O 31, alternate function eCAN-A transmit data output.
33	GPIO30/CANRXA	bidirectional	General-purpose I/O 30, alternate function eCAN-A receive data input.
34	GPIO29/SCITXDA/SCLA/TZ3	bidirectional	General-purpose I/O 29, alternate function SCI-A transmit data, I2C SCL clock line, or ePWM trip-zone 3 input.
35	VSS	power_in	Digital core/logic ground reference.
36	VDDIO	power_in	3.3V digital I/O supply rail for the GPIO buffers; device is designed for single 3.3V-rail operation with no power-sequencing requirement.
37	GPIO26/HRCAP1/SPICLKB	bidirectional	General-purpose I/O 26, alternate function high-resolution capture input 1 or SPI-B clock.
38	TEST2	unconnected	Factory test pin reserved by TI; datasheet states it must be left unconnected.
39	GPIO9/EPWM5B/LINTXA/HRCAP1	bidirectional	General-purpose I/O 9, alternate function ePWM5 B output, LIN transmit data output, or high-resolution capture input 1.
40	GPIO28/SCIRXDA/SDAA/TZ2	bidirectional	General-purpose I/O 28, alternate function SCI-A receive data, I2C SDA data line, or ePWM trip-zone 2 input.
41	GPIO18/SPICLKA/LINTXA/XCLKOUT	bidirectional	General-purpose I/O 18, alternate function SPI-A clock, LIN transmit data output, or buffered output clock XCLKOUT.
42	GPIO17/SPISOMIA/TZ3	bidirectional	General-purpose I/O 17, alternate function SPI-A slave-out/master-in data or ePWM trip-zone 3 input.
43	GPIO8/EPWM5A/ADCSOCAO	bidirectional	General-purpose I/O 8, alternate function ePWM5 A output or ADC-A start-of-conversion output.
44	GPIO25/SPISOMIB	bidirectional	General-purpose I/O 25, alternate function SPI-B slave-out/master-in data.
45	GPIO44	bidirectional	General-purpose I/O 44 with no alternate peripheral function shown for this package.
46	GPIO16/SPISIMOA/TZ2	bidirectional	General-purpose I/O 16, alternate function SPI-A slave-in/master-out data or ePWM trip-zone 2 input.
47	GPIO12/TZ1/SCITXDA/SPISIMOB	bidirectional	General-purpose I/O 12, alternate function ePWM trip-zone 1 input, SCI-A transmit data, or SPI-B slave-in/master-out data.
48	GPIO41/EPWM7B	bidirectional	General-purpose I/O 41, alternate function ePWM7 B output.
49	GPIO7/EPWM4B/SCIRXDA	bidirectional	General-purpose I/O 7, alternate function ePWM4 B output or SCI-A receive data.
50	GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO	bidirectional	General-purpose I/O 6, alternate function ePWM4 A output, ePWM external sync input, or ePWM sync output.
51	X2	output	On-chip crystal oscillator output/feedback pin, used with X1 for the external crystal or resonator network.
52	X1	input	On-chip crystal oscillator input pin, or external clock input, used with X2 for the crystal oscillator circuit.
53	VSS	power_in	Digital core/logic ground reference.
54	VDD	power_in	Digital core logic supply input; internally regulated single-rail device sources this from the on-chip VREG unless bypassed.
55	GPIO19/XCLKIN/SPISTEA/LINRXA/ECAP1	bidirectional	General-purpose I/O 19, alternate function external clock input XCLKIN, SPI-A slave transmit enable, LIN receive data, or eCAP1 input.
56	GPIO39	bidirectional	General-purpose I/O 39 with no alternate peripheral function shown for this package.
57	GPIO38/TCK/XCLKIN	input	Default JTAG test clock (TCK) with internal pull-up, clocked on the rising edge; alternate GPIO38 general-purpose I/O or external clock input XCLKIN function.
58	GPIO37/TDO	output	Default JTAG scan test-data output (TDO), shifts out the selected register contents on the falling edge of TCK with 8-mA drive; alternate GPIO37 general-purpose I/O.
59	GPIO35/TDI	input	Default JTAG test-data input (TDI) with internal pull-up, clocked into the selected register on the rising edge of TCK; alternate GPIO35 general-purpose I/O.
60	GPIO36/TMS	input	Default JTAG test-mode-select input (TMS) with internal pull-up, clocks the TAP controller on the rising edge of TCK; alternate GPIO36 general-purpose I/O.
61	GPIO11/EPWM6B/LINRXA/HRCAP2	bidirectional	General-purpose I/O 11, alternate function ePWM6 B output, LIN receive data, or high-resolution capture input 2.
62	GPIO5/EPWM3B/SPISIMOA/ECAP1	bidirectional	General-purpose I/O 5, alternate function ePWM3 B output, SPI-A slave-in/master-out data, or eCAP1 input.
63	GPIO4/EPWM3A	bidirectional	General-purpose I/O 4, alternate function ePWM3 A output.
64	GPIO40/EPWM7A	bidirectional	General-purpose I/O 40, alternate function ePWM7 A output.
65	GPIO10/EPWM6A/ADCSOCBO	bidirectional	General-purpose I/O 10, alternate function ePWM6 A output or ADC-B start-of-conversion output.
66	GPIO3/EPWM2B/SPISOMIA/COMP2OUT	bidirectional	General-purpose I/O 3, alternate function ePWM2 B output, SPI-A slave-out/master-in data, or comparator 2 output.
67	GPIO2/EPWM2A	bidirectional	General-purpose I/O 2, alternate function ePWM2 A output.
68	GPIO1/EPWM1B/COMP1OUT	bidirectional	General-purpose I/O 1, alternate function ePWM1 B output or comparator 1 output.
69	GPIO0/EPWM1A	bidirectional	General-purpose I/O 0, alternate function ePWM1 A output.
70	VDDIO	power_in	3.3V digital I/O supply rail for the GPIO buffers; device is designed for single 3.3V-rail operation with no power-sequencing requirement.
71	VSS	power_in	Digital core/logic ground reference.
72	VDD	power_in	Digital core logic supply input; internally regulated single-rail device sources this from the on-chip VREG unless bypassed.
73	VREGENZ	input	Active-low internal voltage regulator enable control; tie/leave per application to enable the on-chip VREG for single-rail 3.3V operation or disable it if an external 1.9V core supply is used.
74	GPIO34/COMP2OUT/COMP3OUT	bidirectional	General-purpose I/O 34, alternate function comparator 2 output or comparator 3 output.
75	GPIO15/TZ1/LINRXA/SPISTEB	bidirectional	General-purpose I/O 15, alternate function ePWM trip-zone 1 input, LIN receive data, or SPI-B slave transmit enable.
76	GPIO13/TZ2/SPISOMIB	bidirectional	General-purpose I/O 13, alternate function ePWM trip-zone 2 input or SPI-B slave-out/master-in data.
77	GPIO14/TZ3/LINTXA/SPICLKB	bidirectional	General-purpose I/O 14, alternate function ePWM trip-zone 3 input, LIN transmit data, or SPI-B clock.
78	GPIO20/EQEP1A/COMP1OUT	bidirectional	General-purpose I/O 20, alternate function eQEP1 A quadrature input or comparator 1 output.
79	GPIO21/EQEP1B/COMP2OUT	bidirectional	General-purpose I/O 21, alternate function eQEP1 B quadrature input or comparator 2 output.
80	GPIO24/ECAP1/SPISIMOB	bidirectional	General-purpose I/O 24, alternate function eCAP1 input or SPI-B slave-in/master-out data.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	LQFP-80(12x12)
Category	Embedded Processors & Controllers
Pins	80

CAD (KiCad official)

Symbol: TMS320F28034PNT
Footprint: Package_QFP:LQFP-80_12x12mm_P0.5mm
3D model: LQFP-80(12x12) (KiCad packages3D, STEP)
3D model files: tms320f28034pnt-etched.step / tms320f28034pnt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f28034pnt.step / tms320f28034pnt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (176 pp, sha256 cb9ccecfd6b5c484, retrieved 2026-09-29, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF