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TMS320F28034PNQ

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TMS320F28034PNQ

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)

TMS320F28034PNQ from Texas Instruments, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO22/EQEP1S/LINTXA bidirectional General-purpose I/O 22 or enhanced QEP1 strobe input/output or LIN transmit A output.
2 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO bidirectional General-purpose I/O 32 or I2C data open-drain bidirectional or enhanced PWM external synchronization pulse input or ADC conversion start-of-conversion A output.
3 GPIO33/SCLA/EPWMSYNCO/ADCSOCBO bidirectional General-purpose I/O 33 or I2C clock open-drain bidirectional or enhanced PWM external synchronization pulse output or ADC conversion start-of-conversion B output.
4 GPIO23/EQEP1I/LINRXA bidirectional General-purpose I/O 23 or enhanced QEP1 index input/output or LIN receive A input.
5 GPIO42/COMP1OUT bidirectional General-purpose I/O 42 or comparator 1 direct output.
6 GPIO43/COMP2OUT bidirectional General-purpose I/O 43 or comparator 2 direct output.
7 VDD power_in CPU and logic digital power supply 3.3V nominal.
8 VSS power_in Digital ground.
9 XRS bidirectional Device reset input/output and watchdog reset output with open-drain output buffer and internal pull-up resistance.
10 TRST input JTAG test reset with internal pull-down, high-level active, must remain low during normal device operation.
11 ADCINA7 input ADC group A channel 7 input.
12 ADCINA6/COMP3A/AIO6 input ADC group A channel 6 input or comparator 3A input or analog I/O 6.
13 ADCINA5 input ADC group A channel 5 input.
14 ADCINA4/COMP2A/AIO4 input ADC group A channel 4 input or comparator 2A input or analog I/O 4.
15 ADCINA3 input ADC group A channel 3 input.
16 ADCINA2/COMP1A/AIO2 input ADC group A channel 2 input or comparator 1A input or analog I/O 2.
17 ADCINA1 input ADC group A channel 1 input.
18 ADCINA0/VREFHI input ADC group A channel 0 input or ADC external reference high, not to be used simultaneously.
19 VREFHI input ADC external reference high, only in external reference mode, must not exceed VDDA.
20 VDDA power_in Analog power supply 3.3V nominal with 2.2μF bypass capacitor required nearby.
21 VSSA power_in Analog ground.
22 VREFLO input ADC external reference low, tied to VSSA.
23 ADCINB0 input ADC group B channel 0 input.
24 ADCINB1 input ADC group B channel 1 input.
25 ADCINB2/COMP1B/AIO10 input ADC group B channel 2 input or comparator 1B input or analog I/O 10.
26 ADCINB3 input ADC group B channel 3 input.
27 ADCINB4/COMP2B/AIO12 input ADC group B channel 4 input or comparator 2B input or analog I/O 12.
28 ADCINB5 input ADC group B channel 5 input.
29 ADCINB6/COMP3B/AIO14 input ADC group B channel 6 input or comparator 3B input or analog I/O 14.
30 ADCINB7 input ADC group B channel 7 input.
31 GPIO27/HRCAP2/SPISTEB bidirectional General-purpose I/O 27 or high-resolution capture 2 input or SPI-B slave transmit enable input/output.
32 GPIO31/CANTXA bidirectional General-purpose I/O 31 or CAN transmit output.
33 GPIO30/CANRXA bidirectional General-purpose I/O 30 or CAN receive input.
34 GPIO29/SCITXDA/SCLA/TZ3 bidirectional General-purpose I/O 29 or SCI transmit A output or I2C clock open-drain or trip-zone input 3.
35 VSS power_in Digital ground.
36 VDDIO power_in Digital I/O buffer and flash power supply 3.3V with bypass capacitor required.
37 GPIO26/HRCAP1/SPICLKB bidirectional General-purpose I/O 26 or high-resolution capture 1 input or SPI-B clock input/output.
38 TEST2 input Flash test pin reserved for TI, must be left unconnected.
39 GPIO9/EPWM5B/LINTXA/HRCAP1 bidirectional General-purpose I/O 9 or enhanced PWM 5 output B or LIN transmit A output or high-resolution capture 1 input.
40 GPIO28/SCIRXDA/SDAA/TZ2 bidirectional General-purpose I/O 28 or SCI receive A input or I2C data open-drain or trip-zone input 2.
41 GPIO18/SPICLKA/LINTXA/XCLKOUT bidirectional General-purpose I/O 18 or SPI-A clock input/output or LIN transmit A output or derived XCLKOUT output.
42 GPIO17/SPISOMIA/TZ3 bidirectional General-purpose I/O 17 or SPI-A slave output/master input or trip-zone input 3.
43 GPIO8/EPWM5A/ADCSOCAO bidirectional General-purpose I/O 8 or enhanced PWM 5 output A or ADC conversion start-of-conversion A output.
44 GPIO25/SPISOMIB bidirectional General-purpose I/O 25 or SPI-B slave output/master input (SPI-B only in PN package).
45 GPIO44 bidirectional General-purpose I/O 44.
46 GPIO16/SPISIMOA/TZ2 bidirectional General-purpose I/O 16 or SPI-A slave input/master output or trip-zone input 2.
47 GPIO12/TZ1/SCITXDA/SPISIMOB bidirectional General-purpose I/O 12 or trip-zone input 1 or SCI transmit A output or SPI-B slave input/master output.
48 GPIO41/EPWM7B bidirectional General-purpose I/O 41 or enhanced PWM 7 output B.
49 GPIO7/EPWM4B/SCIRXDA bidirectional General-purpose I/O 7 or enhanced PWM 4 output B or SCI receive A input.
50 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO bidirectional General-purpose I/O 6 or enhanced PWM 4 output A or PWM external synchronization pulse input or PWM synchronization pulse output.
51 X2 output Crystal oscillator output, must connect quartz crystal or ceramic resonator between X1 and X2.
52 X1 input Crystal oscillator 1.8V input, must connect quartz crystal or ceramic resonator between X1 and X2, or ground if unused.
53 VSS power_in Digital ground.
54 VDD power_in CPU and logic digital power supply 3.3V nominal.
55 GPIO19/XCLKIN/SPISTEA/LINRXA/ECAP1 bidirectional General-purpose I/O 19 or external oscillator input or SPI-A slave transmit enable input/output or LIN receive A input or enhanced capture 1 input/output.
56 GPIO39 bidirectional General-purpose I/O 39.
57 GPIO38/TCK/XCLKIN bidirectional General-purpose I/O 38 or JTAG test clock input or external oscillator input (default XCLKIN source).
58 GPIO37/TDO output General-purpose I/O 37 or JTAG test data output with 8mA drive capability.
59 GPIO35/TDI input General-purpose I/O 35 or JTAG test data input with internal pull-up resistor.
60 GPIO36/TMS input General-purpose I/O 36 or JTAG test mode select input with internal pull-up resistor.
61 GPIO11/EPWM6B/LINRXA/HRCAP2 bidirectional General-purpose I/O 11 or enhanced PWM 6 output B or LIN receive A input or high-resolution capture 2 input.
62 GPIO5/EPWM3B/SPISIMOA/ECAP1 bidirectional General-purpose I/O 5 or enhanced PWM 3 output B or SPI-A slave input/master output or enhanced capture 1 input/output.
63 GPIO4/EPWM3A bidirectional General-purpose I/O 4 or enhanced PWM 3 output A and HRPWM channel.
64 GPIO40/EPWM7A bidirectional General-purpose I/O 40 or enhanced PWM 7 output A and HRPWM channel.
65 GPIO10/EPWM6A/ADCSOCBO bidirectional General-purpose I/O 10 or enhanced PWM 6 output A or ADC conversion start-of-conversion B output.
66 GPIO3/EPWM2B/SPISOMIA/COMP2OUT bidirectional General-purpose I/O 3 or enhanced PWM 2 output B or SPI-A slave output/master input or comparator 2 direct output.
67 GPIO2/EPWM2A bidirectional General-purpose I/O 2 or enhanced PWM 2 output A and HRPWM channel.
68 GPIO1/EPWM1B/COMP1OUT bidirectional General-purpose I/O 1 or enhanced PWM 1 output B or comparator 1 direct output.
69 GPIO0/EPWM1A bidirectional General-purpose I/O 0 or enhanced PWM 1 output A and HRPWM channel.
70 VDDIO power_in Digital I/O buffer and flash power supply 3.3V with bypass capacitor required.
71 VSS power_in Digital ground.
72 VDD power_in CPU and logic digital power supply 3.3V nominal.
73 VREGENZ input Internal voltage regulator (VREG) enable with internal pull-down, connect low to enable 1.8V VREG or high to disable and use external 1.8V supply.
74 GPIO34/COMP2OUT/COMP3OUT bidirectional General-purpose I/O 34 or comparator 2 direct output or comparator 3 direct output.
75 GPIO15/TZ1/LINRXA/SPISTEB bidirectional General-purpose I/O 15 or trip-zone input 1 or LIN receive A input or SPI-B slave transmit enable input/output.
76 GPIO13/TZ2/SPISOMIB bidirectional General-purpose I/O 13 or trip-zone input 2 or SPI-B slave output/master input (SPI-B only in PN package).
77 GPIO14/TZ3/LINTXA/SPICLKB bidirectional General-purpose I/O 14 or trip-zone input 3 or LIN transmit A output or SPI-B clock input/output.
78 GPIO20/EQEP1A/COMP1OUT bidirectional General-purpose I/O 20 or enhanced QEP 1 input A or comparator 1 direct output.
79 GPIO21/EQEP1B/COMP2OUT bidirectional General-purpose I/O 21 or enhanced QEP 1 input B or comparator 2 direct output.
80 GPIO24/ECAP1/SPISIMOB bidirectional General-purpose I/O 24 or enhanced capture 1 input/output or SPI-B slave input/master output (SPI-B only in PN package).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-80(12x12)
Category Embedded Processors & Controllers
Pins 80

CAD (KiCad official)

  • Symbol: TMS320F28034PNQ
  • Footprint: Package_QFP:LQFP-80_12x12mm_P0.5mm
  • 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)
  • 3D model files: tms320f28034pnq-etched.step / tms320f28034pnq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f28034pnq.step / tms320f28034pnq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (176 pp, sha256 cb9ccecfd6b5c484, retrieved 2026-10-01, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF