component
TMS320F28033PAGS
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTMS320F28033PAGS
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · TQFP-64(10x10)
TMS320F28033PAGS from Texas Instruments, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GPIO22/EQEP1S/LINTXA | bidirectional | GPIO22 with internal pull-up enabled after reset; alternates are EQEP1 strobe (I/O) and LIN transmit (O), and inputs are not 5 V tolerant. |
| 2 | GPIO32/SDAA/EPWMSYNCI/ADCSOCAO | bidirectional | GPIO32 with internal pull-up; alternates are I2C-A data (open-drain), ePWM sync input, and ADC SOC-A output; inputs are not 5 V tolerant. |
| 3 | GPIO33/SCLA/EPWMSYNCO/ADCSOCBO | bidirectional | GPIO33 with internal pull-up; alternates are I2C-A clock (open-drain), ePWM sync output, and ADC SOC-B output; inputs are not 5 V tolerant. |
| 4 | GPIO23/EQEP1I/LINRXA | bidirectional | GPIO23 with internal pull-up; alternates are EQEP1 index (I/O) and LIN receive (I); inputs are not 5 V tolerant. |
| 5 | VDD | power_in | CPU and logic digital supply; when the internal VREG is used, a 1.2 µF (minimum) capacitor is required on each VDD pin, and when supplied externally the range is 1.71 V to 1.995 V (1.8 V nominal). |
| 6 | VSS | power_in | Digital ground pin. |
| 7 | XRS | bidirectional | Device reset input and watchdog reset output, an open-drain pin with internal pull-up; a 2.2 kΩ to 10 kΩ resistor to VDDIO is required and any noise filter capacitor to VSS must be 100 nF or less. |
| 8 | TRST | input | JTAG test reset with internal pull-down; must be held low during normal operation and typically needs an external pull-up of about 2.2 kΩ, sized to the debugger pod. |
| 9 | ADCINA7 | passive | ADC group A channel 7 analog input, 0 V to 3.3 V full scale with the internal reference (or VREFHI/VREFLO with an external reference). |
| 10 | ADCINA6/COMP3A/AIO6 | passive | ADC group A channel 6 analog input, also comparator 3A input and digital AIO6; AIO pins have no internal pull-up. |
| 11 | ADCINA4/COMP2A/AIO4 | passive | ADC group A channel 4 analog input, also comparator 2A input and digital AIO4; AIO pins have no internal pull-up. |
| 12 | ADCINA3 | passive | ADC group A channel 3 analog input. |
| 13 | ADCINA2/COMP1A/AIO2 | passive | ADC group A channel 2 analog input, also comparator 1A input and digital AIO2; AIO pins have no internal pull-up. |
| 14 | ADCINA1 | passive | ADC group A channel 1 analog input. |
| 15 | ADCINA0/VREFHI | passive | ADC group A channel 0 input that shares this pin with the external ADC reference high VREFHI (external reference mode only), so the two cannot be used together and VREFHI must not exceed VDDA. |
| 16 | VDDA | power_in | Analog supply, 2.97 V to 3.63 V (3.3 V nominal), with about a 2.2 µF capacitor placed near this pin. |
| 17 | VSSA/VREFLO | power_in | Analog ground; on the 64-pin PAG package the ADC low reference VREFLO is always connected to VSSA. |
| 18 | ADCINB0 | passive | ADC group B channel 0 analog input. |
| 19 | ADCINB1 | passive | ADC group B channel 1 analog input. |
| 20 | ADCINB2/COMP1B/AIO10 | passive | ADC group B channel 2 analog input, also comparator 1B input and digital AIO10; AIO pins have no internal pull-up. |
| 21 | ADCINB3 | passive | ADC group B channel 3 analog input. |
| 22 | ADCINB4/COMP2B/AIO12 | passive | ADC group B channel 4 analog input, also comparator 2B input and digital AIO12; AIO pins have no internal pull-up. |
| 23 | ADCINB6/COMP3B/AIO14 | passive | ADC group B channel 6 analog input, also comparator 3B input and digital AIO14; AIO pins have no internal pull-up. |
| 24 | ADCINB7 | passive | ADC group B channel 7 analog input. |
| 25 | GPIO31/CANTXA | bidirectional | GPIO31 with internal pull-up; alternate function is eCAN transmit output CANTXA. |
| 26 | GPIO30/CANRXA | bidirectional | GPIO30 with internal pull-up; alternate function is eCAN receive input CANRXA. |
| 27 | GPIO29/SCITXDA/SCLA/TZ3 | bidirectional | GPIO29 with internal pull-up; alternates are SCI-A transmit (O), I2C-A clock (open-drain), and trip-zone input TZ3. |
| 28 | VSS | power_in | Digital ground pin. |
| 29 | VDDIO | power_in | Digital I/O buffer and flash supply, 2.97 V to 3.63 V (3.3 V nominal); a decoupling capacitor is required on this pin. |
| 30 | TEST2 | unconnected | Reserved for TI testing; must remain unconnected. |
| 31 | GPIO9/EPWM5B/LINTXA/HRCAP1 | bidirectional | GPIO9 with internal pull-up; alternates are ePWM5B output, LIN transmit (O), and high-resolution capture 1 input. |
| 32 | GPIO28/SCIRXDA/SDAA/TZ2 | bidirectional | GPIO28 with internal pull-up; alternates are SCI-A receive (I), I2C-A data (open-drain), and trip-zone input TZ2. |
| 33 | GPIO18/SPICLKA/LINTXA/XCLKOUT | bidirectional | GPIO18 with internal pull-up; alternates are SPI-A clock (I/O), LIN transmit (O), and XCLKOUT, which defaults to SYSCLKOUT/4 at reset. |
| 34 | GPIO17/SPISOMIA/TZ3 | bidirectional | GPIO17 with internal pull-up; alternates are SPI-A slave-out/master-in (I/O) and trip-zone input TZ3. |
| 35 | GPIO8/EPWM5A/ADCSOCAO | bidirectional | GPIO8 with internal pull-up; alternates are ePWM5A output with HRPWM channel and ADC SOC-A output. |
| 36 | GPIO16/SPISIMOA/TZ2 | bidirectional | GPIO16 with internal pull-up; alternates are SPI-A slave-in/master-out (I/O) and trip-zone input TZ2. |
| 37 | GPIO12/TZ1/SCITXDA | bidirectional | GPIO12 with internal pull-up; alternates are trip-zone input TZ1 and SCI-A transmit (O); SPI-B on this pin is not available in the PAG package. |
| 38 | GPIO7/EPWM4B/SCIRXDA | bidirectional | GPIO7 with internal pull-up; alternates are ePWM4B output and SCI-A receive input. |
| 39 | GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO | bidirectional | GPIO6 with internal pull-up; alternates are ePWM4A output with HRPWM channel, external ePWM sync input, and external ePWM sync output. |
| 40 | X2 | output | On-chip crystal oscillator output; a crystal or ceramic resonator must be connected between X1 and X2, and X2 must be left unconnected if unused. |
| 41 | X1 | input | 1.8 V on-chip crystal oscillator input that must not be driven with a 3.3 V level; tie to GND if the oscillator is unused. |
| 42 | VSS | power_in | Digital ground pin. |
| 43 | VDD | power_in | CPU and logic digital supply; when the internal VREG is used, a 1.2 µF (minimum) capacitor is required on each VDD pin. |
| 44 | GPIO19/XCLKIN/SPISTEA/LINRXA/ECAP1 | bidirectional | GPIO19 with internal pull-up; alternates are external oscillator input XCLKIN, SPI-A slave transmit enable (I/O), LIN receive (I), and ECAP1 (I/O); the XCLKIN path is not controlled by this pin's mux. |
| 45 | GPIO38/TCK/XCLKIN | bidirectional | GPIO38 with internal pull-up; alternates are JTAG test clock TCK and external oscillator input XCLKIN, and TCK is needed for JTAG debug so an external clock on this pin may need a disable path. |
| 46 | GPIO37/TDO | tri_state | GPIO37 with JTAG test data output TDO (O/Z), providing 8 mA drive, with data shifted out on the falling edge of TCK. |
| 47 | GPIO35/TDI | bidirectional | GPIO35 with internal pull-up; JTAG test data input TDI, latched on the rising edge of TCK. |
| 48 | GPIO36/TMS | bidirectional | GPIO36 with internal pull-up; JTAG test mode select TMS, latched by the TAP controller on the rising edge of TCK. |
| 49 | GPIO11/EPWM6B/LINRXA/HRCAP2 | bidirectional | GPIO11 with internal pull-up; alternates are ePWM6B output, LIN receive (I), and high-resolution capture 2 input. |
| 50 | GPIO5/EPWM3B/SPISIMOA/ECAP1 | bidirectional | GPIO5 with internal pull-up; alternates are ePWM3B output, SPI-A slave-in/master-out (I/O), and ECAP1 (I/O). |
| 51 | GPIO4/EPWM3A | bidirectional | GPIO4 with internal pull-up; alternate function is ePWM3A output with HRPWM channel. |
| 52 | GPIO10/EPWM6A/ADCSOCBO | bidirectional | GPIO10 with internal pull-up; alternates are ePWM6A output with HRPWM channel and ADC SOC-B output. |
| 53 | GPIO3/EPWM2B/SPISOMIA/COMP2OUT | bidirectional | GPIO3 with internal pull-up; alternates are ePWM2B output, SPI-A slave-out/master-in (I/O), and comparator 2 direct output. |
| 54 | GPIO2/EPWM2A | bidirectional | GPIO2 with internal pull-up; alternate function is ePWM2A output with HRPWM channel. |
| 55 | GPIO1/EPWM1B/COMP1OUT | bidirectional | GPIO1 with internal pull-up; alternates are ePWM1B output and comparator 1 direct output. |
| 56 | GPIO0/EPWM1A | bidirectional | GPIO0 with internal pull-up; alternate function is ePWM1A output with HRPWM channel. |
| 57 | VDDIO | power_in | Digital I/O buffer and flash supply, 2.97 V to 3.63 V (3.3 V nominal); a decoupling capacitor is required on this pin. |
| 58 | VSS | power_in | Digital ground pin. |
| 59 | VDD | power_in | CPU and logic digital supply; when the internal VREG is used, a 1.2 µF (minimum) capacitor is required on each VDD pin. |
| 60 | VREGENZ | input | Internal regulator enable with internal pull-down: tie to VSS to enable the 1.8 V VREG, or to VDDIO to disable it and supply 1.8 V externally. |
| 61 | GPIO34/COMP2OUT/COMP3OUT | bidirectional | GPIO34 with internal pull-up; alternates are comparator 2 direct output and comparator 3 direct output; GPIO34 can glitch during power-up when VREG is used. |
| 62 | GPIO20/EQEP1A/COMP1OUT | bidirectional | GPIO20 with internal pull-up; alternates are EQEP1 input A (I) and comparator 1 direct output. |
| 63 | GPIO21/EQEP1B/COMP2OUT | bidirectional | GPIO21 with internal pull-up; alternates are EQEP1 input B (I) and comparator 2 direct output. |
| 64 | GPIO24/ECAP1 | bidirectional | GPIO24 with internal pull-up; alternate function is enhanced capture 1 (I/O); SPI-B on this pin is not available in the PAG package. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
CAD (KiCad official)
- Symbol:
TMS320F28033PAGS - Footprint:
Package_QFP:TQFP-64_10x10mm_P0.5mm - 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
tms320f28033pags-etched.step/tms320f28033pags-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tms320f28033pags.step/tms320f28033pags.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (176 pp, sha256
cb9ccecfd6b5c484, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).