component
TMS320F28033PAGQ
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTMS320F28033PAGQ
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · TQFP-64(10x10)
TMS320F28033PAGQ from Texas Instruments, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GPIO22/EQEP1S/LINTXA | bidirectional | General-purpose I/O 22 (default GPIO) with internal pull-up enabled after reset; alternate functions are eQEP1 strobe (I/O) and LIN transmit (output). |
| 2 | GPIO32/SDAA/EPWMSYNCI/ADCSOCAO | bidirectional | General-purpose I/O 32 with internal pull-up enabled after reset; when selected as I2C-A SDA it is an open-drain bidirectional port, with alternate EPWMSYNCI input and ADCSOCAO output. |
| 3 | GPIO33/SCLA/EPWMSYNCO/ADCSOCBO | bidirectional | General-purpose I/O 33 with internal pull-up enabled after reset; when selected as I2C-A SCL it is an open-drain bidirectional port, with alternate EPWMSYNCO and ADCSOCBO outputs. |
| 4 | GPIO23/EQEP1I/LINRXA | bidirectional | General-purpose I/O 23 with internal pull-up enabled after reset; alternate functions are eQEP1 index (I/O) and LIN receive (input). |
| 5 | VDD | power_in | CPU and logic digital supply; when the internal VREG is used, place a 1.2 µF (minimum) capacitor between each VDD pin and ground as close as possible to the pin. |
| 6 | VSS | power_in | Digital ground pin. |
| 7 | XRS | bidirectional | Device reset input and watchdog reset output on an open-drain pin with internal pull-up; connect a 2.2 kΩ to 10 kΩ resistor between XRS and VDDIO, and any noise capacitor to VSS must be 100 nF or less. |
| 8 | TRST | input | JTAG test reset with internal pull-down; it must be held low during normal operation and an external pull-up (about 2.2 kΩ typical, to be verified per debugger) is required. |
| 9 | ADCINA7 | input | ADC group A channel 7 analog input. |
| 10 | ADCINA6/COMP3A/AIO6 | bidirectional | ADC group A channel 6 analog input, also comparator 3A input and digital AIO6; AIO pins have no internal pull-up and digital function is disabled by default at reset. |
| 11 | ADCINA4/COMP2A/AIO4 | bidirectional | ADC group A channel 4 analog input, also comparator 2A input and digital AIO4; AIO pins have no internal pull-up and digital function is disabled by default at reset. |
| 12 | ADCINA3 | input | ADC group A channel 3 analog input. |
| 13 | ADCINA2/COMP1A/AIO2 | bidirectional | ADC group A channel 2 analog input, also comparator 1A input and digital AIO2; AIO pins have no internal pull-up and digital function is disabled by default at reset. |
| 14 | ADCINA1 | input | ADC group A channel 1 analog input. |
| 15 | ADCINA0/VREFHI | input | ADC group A channel 0 analog input, shared with the ADC external high reference VREFHI (external reference mode only) so the two cannot be used simultaneously; VREFHI must not exceed VDDA in internal or external reference modes. |
| 16 | VDDA | power_in | Analog supply, 2.97 V to 3.63 V (3.3 V nominal); place a 2.2 µF capacitor (typical) near this pin. |
| 17 | VSSA/VREFLO | power_in | Analog ground; the ADC external low reference VREFLO is always connected to VSSA on the PAG package. |
| 18 | ADCINB0 | input | ADC group B channel 0 analog input. |
| 19 | ADCINB1 | input | ADC group B channel 1 analog input. |
| 20 | ADCINB2/COMP1B/AIO10 | bidirectional | ADC group B channel 2 analog input, also comparator 1B input and digital AIO10; AIO pins have no internal pull-up. |
| 21 | ADCINB3 | input | ADC group B channel 3 analog input. |
| 22 | ADCINB4/COMP2B/AIO12 | bidirectional | ADC group B channel 4 analog input, also comparator 2B input and digital AIO12; AIO pins have no internal pull-up. |
| 23 | ADCINB6/COMP3B/AIO14 | bidirectional | ADC group B channel 6 analog input, also comparator 3B input and digital AIO14; AIO pins have no internal pull-up. |
| 24 | ADCINB7 | input | ADC group B channel 7 analog input. |
| 25 | GPIO31/CANTXA | bidirectional | General-purpose I/O 31 with internal pull-up enabled after reset; alternate function is eCAN-A transmit output (CANTXA). |
| 26 | GPIO30/CANRXA | bidirectional | General-purpose I/O 30 with internal pull-up enabled after reset; alternate function is eCAN-A receive input (CANRXA). |
| 27 | GPIO29/SCITXDA/SCLA/TZ3 | bidirectional | General-purpose I/O 29 (Group 2, 8 mA drive) with internal pull-up enabled after reset; alternate functions are SCI-A transmit, I2C-A SCL (open-drain) and trip-zone input TZ3. |
| 28 | VSS | power_in | Digital ground pin. |
| 29 | VDDIO | power_in | Digital I/O buffer and flash supply, 2.97 V to 3.63 V (3.3 V nominal); place a decoupling capacitor on this pin, value set by the system regulator solution. |
| 30 | TEST2 | bidirectional | Reserved for TI testing; must be left unconnected. |
| 31 | GPIO9/EPWM5B/LINTXA/HRCAP1 | bidirectional | General-purpose I/O 9 with internal pull-up enabled after reset; alternate functions are ePWM5B output, LIN transmit output and high-resolution capture input HRCAP1. |
| 32 | GPIO28/SCIRXDA/SDAA/TZ2 | bidirectional | General-purpose I/O 28 (Group 2, 8 mA drive) with internal pull-up enabled after reset; alternate functions are SCI-A receive, I2C-A SDA (open-drain) and trip-zone input TZ2. |
| 33 | GPIO18/SPICLKA/LINTXA/XCLKOUT | bidirectional | General-purpose I/O 18 (Group 2, 8 mA drive) with internal pull-up enabled after reset; alternate functions are SPI-A clock, LIN transmit and XCLKOUT (SYSCLKOUT divided by 1, 2 or 4). |
| 34 | GPIO17/SPISOMIA/TZ3 | bidirectional | General-purpose I/O 17 with internal pull-up enabled after reset; alternate functions are SPI-A slave output/master input and trip-zone input TZ3. |
| 35 | GPIO8/EPWM5A/ADCSOCAO | bidirectional | General-purpose I/O 8 with internal pull-up disabled at reset on PWM pins; alternate functions are ePWM5A output (with HRPWM) and ADC start-of-conversion output ADCSOCAO. |
| 36 | GPIO16/SPISIMOA/TZ2 | bidirectional | General-purpose I/O 16 (Group 2, 8 mA drive) with internal pull-up enabled after reset; alternate functions are SPI-A slave input/master output and trip-zone input TZ2. |
| 37 | GPIO12/TZ1/SCITXDA | bidirectional | General-purpose I/O 12 with internal pull-up enabled after reset; alternate functions are trip-zone input TZ1 and SCI-A transmit output (the SPISIMOB alternate is not available on the PAG package). |
| 38 | GPIO7/EPWM4B/SCIRXDA | bidirectional | General-purpose I/O 7 with internal pull-up enabled after reset; alternate functions are ePWM4B output and SCI-A receive input. |
| 39 | GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO | bidirectional | General-purpose I/O 6 with internal pull-up disabled at reset on PWM pins; alternate functions are ePWM4A output (with HRPWM), external sync input EPWMSYNCI and sync output EPWMSYNCO. |
| 40 | X2 | output | On-chip crystal oscillator output; a crystal or ceramic resonator must be connected between X1 and X2, and X2 must be left unconnected if unused. |
| 41 | X1 | input | 1.8 V on-chip crystal oscillator input that must never be driven with a 3.3 V signal; it must be tied to GND if unused and is not a single-ended clock input. |
| 42 | VSS | power_in | Digital ground pin. |
| 43 | VDD | power_in | CPU and logic digital supply; when the internal VREG is used, place a 1.2 µF (minimum) capacitor between this pin and ground. |
| 44 | GPIO19/XCLKIN/SPISTEA/LINRXA/ECAP1 | bidirectional | General-purpose I/O 19 (Group 2, 8 mA drive) with internal pull-up enabled after reset; alternate function XCLKIN external oscillator input is not controlled by the mux and must not be enabled as a clock path if used for other functions, and other alternates are SPI-A STE, LIN receive and eCAP1. |
| 45 | GPIO38/TCK/XCLKIN | bidirectional | General-purpose I/O 38 with JTAG test clock TCK input (internal pull-up) and XCLKIN external oscillator input; the default XCLKIN source, and the XCLKIN path must be disabled during JTAG debug to avoid TCK contention. |
| 46 | GPIO37/TDO | bidirectional | General-purpose I/O 37 (Group 2, 8 mA drive) that is the JTAG scan data output TDO; glitches may occur on power-up when the internal VREG is used. |
| 47 | GPIO35/TDI | bidirectional | General-purpose I/O 35 that is the JTAG test data input TDI with internal pull-up; glitches may occur on power-up when the internal VREG is used. |
| 48 | GPIO36/TMS | bidirectional | General-purpose I/O 36 (Group 2, 8 mA drive) that is the JTAG test mode select TMS input with internal pull-up; glitches may occur on power-up when the internal VREG is used. |
| 49 | GPIO11/EPWM6B/LINRXA/HRCAP2 | bidirectional | General-purpose I/O 11 with internal pull-up disabled at reset on PWM pins; alternate functions are ePWM6B output, LIN receive input and HRCAP2 input. |
| 50 | GPIO5/EPWM3B/SPISIMOA/ECAP1 | bidirectional | General-purpose I/O 5 with internal pull-up disabled at reset on PWM pins; alternate functions are ePWM3B output, SPI-A slave input/master output and eCAP1 I/O. |
| 51 | GPIO4/EPWM3A | bidirectional | General-purpose I/O 4 with internal pull-up disabled at reset on PWM pins; alternate function is ePWM3A output (with HRPWM). |
| 52 | GPIO10/EPWM6A/ADCSOCBO | bidirectional | General-purpose I/O 10 with internal pull-up disabled at reset on PWM pins; alternate functions are ePWM6A output (with HRPWM) and ADC start-of-conversion output ADCSOCBO. |
| 53 | GPIO3/EPWM2B/SPISOMIA/COMP2OUT | bidirectional | General-purpose I/O 3 with internal pull-up disabled at reset on PWM pins; alternate functions are ePWM2B output, SPI-A slave output/master input and comparator 2 direct output COMP2OUT. |
| 54 | GPIO2/EPWM2A | bidirectional | General-purpose I/O 2 with internal pull-up disabled at reset on PWM pins; alternate function is ePWM2A output (with HRPWM). |
| 55 | GPIO1/EPWM1B/COMP1OUT | bidirectional | General-purpose I/O 1 with internal pull-up disabled at reset on PWM pins; alternate functions are ePWM1B output and comparator 1 direct output COMP1OUT. |
| 56 | GPIO0/EPWM1A | bidirectional | General-purpose I/O 0 with internal pull-up disabled at reset on PWM pins; alternate function is ePWM1A output (with HRPWM). |
| 57 | VDDIO | power_in | Digital I/O buffer and flash supply, 2.97 V to 3.63 V (3.3 V nominal); place a decoupling capacitor on this pin. |
| 58 | VSS | power_in | Digital ground pin. |
| 59 | VDD | power_in | CPU and logic digital supply; when the internal VREG is used, place a 1.2 µF (minimum) capacitor between this pin and ground. |
| 60 | VREGENZ | input | Internal regulator enable with internal pull-down: connect to VSS (low) to enable the internal 1.8 V VREG, or to VDDIO (high) to disable it and supply 1.8 V to VDD externally. |
| 61 | GPIO34/COMP2OUT/COMP3OUT | bidirectional | General-purpose I/O 34 with internal pull-up enabled after reset; alternate functions are comparator 2 direct output COMP2OUT and comparator 3 direct output COMP3OUT; glitches may occur on power-up when the internal VREG is used. |
| 62 | GPIO20/EQEP1A/COMP1OUT | bidirectional | General-purpose I/O 20 with internal pull-up enabled after reset; alternate functions are eQEP1 input A and comparator 1 direct output COMP1OUT. |
| 63 | GPIO21/EQEP1B/COMP2OUT | bidirectional | General-purpose I/O 21 with internal pull-up enabled after reset; alternate functions are eQEP1 input B and comparator 2 direct output COMP2OUT. |
| 64 | GPIO24/ECAP1 | bidirectional | General-purpose I/O 24 with internal pull-up enabled after reset; alternate function is eCAP1 I/O (the SPISIMOB alternate is not available on the PAG package). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
CAD (KiCad official)
- Symbol:
TMS320F28033PAGQ - Footprint:
Package_QFP:TQFP-64_10x10mm_P0.5mm - 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
tms320f28033pagq-etched.step/tms320f28033pagq-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tms320f28033pagq.step/tms320f28033pagq.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (176 pp, sha256
cb9ccecfd6b5c484, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).