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TMS320F28032PNT

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TMS320F28032PNT

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)

TMS320F28032PNT from Texas Instruments, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO22/EQEP1S/LINTXA bidirectional General-purpose I/O 22 with internal pull-up enabled after reset; alternates are EQEP1 strobe (I/O) and LIN transmit (O). Inputs are not 5 V tolerant.
2 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO bidirectional General-purpose I/O 32; alternates are I2C-A data (open-drain), ePWM external sync input, and ADC SOC-A output. Inputs are not 5 V tolerant.
3 GPIO33/SCLA/EPWMSYNCO/ADCSOCBO bidirectional General-purpose I/O 33; alternates are I2C-A clock (open-drain), ePWM external sync output, and ADC SOC-B output. Inputs are not 5 V tolerant.
4 GPIO23/EQEP1I/LINRXA bidirectional General-purpose I/O 23 with internal pull-up enabled after reset; alternates are EQEP1 index (I/O) and LIN receive (I). Inputs are not 5 V tolerant.
5 GPIO42/COMP1OUT bidirectional General-purpose I/O 42 with internal pull-up enabled after reset; alternate is the direct output of comparator 1 (O).
6 GPIO43/COMP2OUT bidirectional General-purpose I/O 43 with internal pull-up enabled after reset; alternate is the direct output of comparator 2 (O).
7 VDD power_in CPU and logic digital supply; 1.71 V to 1.995 V when the internal VREG is disabled and VDD is externally supplied, and a 1.2 µF minimum capacitor per VDD pin when the internal VREG is used.
8 VSS power_in Digital ground pin.
9 XRS bidirectional Device reset input and watchdog reset output; open-drain with internal pull-up, driven low on power-up, brown-out, and watchdog reset; a 2.2 kΩ to 10 kΩ resistor between XRS and VDDIO is recommended, and any noise filter capacitor to VSS should be 100 nF or less.
10 TRST input JTAG test reset with internal pull-down; must be held low during normal operation and requires an external pull-up (about 2.2 kΩ is typical).
11 ADCINA7 input ADC group A channel 7 analog input (0 V to 3.3 V full scale with the internal reference).
12 ADCINA6/COMP3A/AIO6 input ADC group A channel 6 analog input, also comparator 3A input; the AIO6 digital I/O function is available when selected in AIOMUX1.
13 ADCINA5 input ADC group A channel 5 analog input.
14 ADCINA4/COMP2A/AIO4 input ADC group A channel 4 analog input, also comparator 2A input; the AIO4 digital I/O function is available when selected in AIOMUX1.
15 ADCINA3 input ADC group A channel 3 analog input.
16 ADCINA2/COMP1A/AIO2 input ADC group A channel 2 analog input, also comparator 1A input; the AIO2 digital I/O function is available when selected in AIOMUX1.
17 ADCINA1 input ADC group A channel 1 analog input.
18 ADCINA0 input ADC group A channel 0 analog input.
19 VREFHI input ADC external high reference, used only in external reference mode; it must not exceed VDDA in internal or external reference mode.
20 VDDA power_in Analog supply, 2.97 V to 3.63 V recommended; a 2.2 µF typical capacitor is connected near this pin.
21 VSSA power_in Analog ground pin.
22 VREFLO input ADC external low reference, used in external reference mode.
23 ADCINB0 input ADC group B channel 0 analog input.
24 ADCINB1 input ADC group B channel 1 analog input.
25 ADCINB2/COMP1B/AIO10 input ADC group B channel 2 analog input, also comparator 1B input; the AIO10 digital I/O function is available when selected in AIOMUX1.
26 ADCINB3 input ADC group B channel 3 analog input.
27 ADCINB4/COMP2B/AIO12 input ADC group B channel 4 analog input, also comparator 2B input; the AIO12 digital I/O function is available when selected in AIOMUX1.
28 ADCINB5 input ADC group B channel 5 analog input.
29 ADCINB6/COMP3B/AIO14 input ADC group B channel 6 analog input, also comparator 3B input; the AIO14 digital I/O function is available when selected in AIOMUX1.
30 ADCINB7 input ADC group B channel 7 analog input.
31 GPIO27/HRCAP2/SPISTEB bidirectional General-purpose I/O 27 with internal pull-up enabled after reset; alternates are HRCAP2 input and SPI-B slave transmit enable (I/O).
32 GPIO31/CANTXA bidirectional General-purpose I/O 31 with internal pull-up enabled after reset; alternate is CAN-A transmit (O).
33 GPIO30/CANRXA bidirectional General-purpose I/O 30 with internal pull-up enabled after reset; alternate is CAN-A receive (I).
34 GPIO29/SCITXDA/SCLA/TZ3 bidirectional General-purpose I/O 29 with internal pull-up enabled after reset; alternates are SCI-A transmit (O), I2C-A clock (open-drain), and trip-zone input 3.
35 VSS power_in Digital ground pin.
36 VDDIO power_in Digital I/O buffer and flash supply, 2.97 V to 3.63 V recommended; decoupling capacitor required on each pin.
37 GPIO26/HRCAP1/SPICLKB bidirectional General-purpose I/O 26 with internal pull-up enabled after reset; alternates are HRCAP1 input and SPI-B clock (I/O).
38 TEST2 unconnected Test pin reserved for TI; must be left unconnected.
39 GPIO9/EPWM5B/LINTXA/HRCAP1 bidirectional General-purpose I/O 9; alternates are ePWM5B output (PWM pins have no pull-up at reset), LIN transmit (O), and HRCAP1 input.
40 GPIO28/SCIRXDA/SDAA/TZ2 bidirectional General-purpose I/O 28 with internal pull-up enabled after reset; alternates are SCI-A receive (I), I2C-A data (open-drain), and trip-zone input 2.
41 GPIO18/SPICLKA/LINTXA/XCLKOUT bidirectional General-purpose I/O 18; alternates are SPI-A clock (I/O), LIN transmit (O), and XCLKOUT (O/Z, derived from SYSCLKOUT, reset value SYSCLKOUT/4).
42 GPIO17/SPISOMIA/TZ3 bidirectional General-purpose I/O 17 with internal pull-up enabled after reset; alternates are SPI-A slave output (I/O) and trip-zone input 3.
43 GPIO8/EPWM5A/ADCSOCAO bidirectional General-purpose I/O 8; alternates are ePWM5A output (PWM pins have no pull-up at reset) and ADC SOC-A output (O).
44 GPIO25/SPISOMIB bidirectional General-purpose I/O 25 with internal pull-up enabled after reset; alternate is SPI-B slave output (I/O).
45 GPIO44 bidirectional General-purpose I/O 44 with internal pull-up enabled after reset; no peripheral alternate function is listed.
46 GPIO16/SPISIMOA/TZ2 bidirectional General-purpose I/O 16 with internal pull-up enabled after reset; alternates are SPI-A slave input (I/O) and trip-zone input 2. This pin is in output group 2 (8 mA source/sink capability).
47 GPIO12/TZ1/SCITXDA/SPISIMOB bidirectional General-purpose I/O 12 with internal pull-up enabled after reset; alternates are trip-zone input 1, SCI-A transmit (O), and SPI-B slave input (I/O, PN package only).
48 GPIO41/EPWM7B bidirectional General-purpose I/O 41; alternate is ePWM7B output (PWM pins have no pull-up at reset).
49 GPIO7/EPWM4B/SCIRXDA bidirectional General-purpose I/O 7; alternates are ePWM4B output (PWM pins have no pull-up at reset) and SCI-A receive (I).
50 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO bidirectional General-purpose I/O 6; alternates are ePWM4A output with HRPWM channel (PWM pins have no pull-up at reset), external ePWM sync input, and external ePWM sync output.
51 X2 output On-chip crystal oscillator output; must be connected to a crystal or ceramic resonator with X1 and left unconnected if not used.
52 X1 input 1.8 V on-chip crystal oscillator input; must not be driven with a 3.3 V level, and must be tied to GND if unused.
53 VSS power_in Digital ground pin.
54 VDD power_in CPU and logic digital supply pin (see VDD on pin 7 for voltage and decoupling requirements).
55 GPIO19/XCLKIN/SPISTEA/LINRXA/ECAP1 bidirectional General-purpose I/O 19; alternates are external oscillator clock input XCLKIN, SPI-A slave transmit enable (I/O), LIN receive (I), and ECAP1 (I/O). Power-up glitches can occur on this pin when using the internal VREG.
56 GPIO39 bidirectional General-purpose I/O 39 with internal pull-up enabled after reset; no peripheral alternate function is listed.
57 GPIO38/TCK/XCLKIN bidirectional General-purpose I/O 38; alternates are JTAG test clock TCK with internal pull-up and external oscillator input XCLKIN (disable the XCLKIN path during JTAG debug).
58 GPIO37/TDO bidirectional General-purpose I/O 37; alternate is JTAG test data output TDO (O/Z, 8 mA drive), shifted out on TCK falling edge.
59 GPIO35/TDI bidirectional General-purpose I/O 35; alternate is JTAG test data input TDI with internal pull-up, sampled on TCK rising edge.
60 GPIO36/TMS bidirectional General-purpose I/O 36; alternate is JTAG test mode select TMS with internal pull-up, sampled on TCK rising edge.
61 GPIO11/EPWM6B/LINRXA/HRCAP2 bidirectional General-purpose I/O 11; alternates are ePWM6B output (PWM pins have no pull-up at reset), LIN receive (I), and HRCAP2 input.
62 GPIO5/EPWM3B/SPISIMOA/ECAP1 bidirectional General-purpose I/O 5; alternates are ePWM3B output (PWM pins have no pull-up at reset), SPI-A slave input (I/O), and ECAP1 (I/O).
63 GPIO4/EPWM3A bidirectional General-purpose I/O 4; alternate is ePWM3A output with HRPWM channel (PWM pins have no pull-up at reset).
64 GPIO40/EPWM7A bidirectional General-purpose I/O 40; alternate is ePWM7A output with HRPWM channel (PWM pins have no pull-up at reset).
65 GPIO10/EPWM6A/ADCSOCBO bidirectional General-purpose I/O 10; alternates are ePWM6A output with HRPWM channel (PWM pins have no pull-up at reset) and ADC SOC-B output (O).
66 GPIO3/EPWM2B/SPISOMIA/COMP2OUT bidirectional General-purpose I/O 3 with internal pull-up enabled after reset; alternates are ePWM2B output, SPI-A slave output (I/O), and comparator 2 direct output (O).
67 GPIO2/EPWM2A bidirectional General-purpose I/O 2; alternate is ePWM2A output with HRPWM channel (PWM pins have no pull-up at reset).
68 GPIO1/EPWM1B/COMP1OUT bidirectional General-purpose I/O 1; alternates are ePWM1B output (PWM pins have no pull-up at reset) and comparator 1 direct output (O).
69 GPIO0/EPWM1A bidirectional General-purpose I/O 0; alternate is ePWM1A output with HRPWM channel (PWM pins have no pull-up at reset).
70 VDDIO power_in Digital I/O buffer and flash supply pin (see VDDIO on pin 36).
71 VSS power_in Digital ground pin.
72 VDD power_in CPU and logic digital supply pin (see VDD on pin 7 for voltage and decoupling requirements).
73 VREGENZ input Internal regulator enable with internal pull-down: tie to VSS to enable the internal 1.8 V VREG, or to VDDIO to disable it and use an external 1.8 V supply on VDD.
74 GPIO34/COMP2OUT/COMP3OUT bidirectional General-purpose I/O 34 with internal pull-up enabled after reset; alternates are comparator 2 direct output and comparator 3 direct output (O). Power-up glitches can occur on this pin when using the internal VREG.
75 GPIO15/TZ1/LINRXA/SPISTEB bidirectional General-purpose I/O 15 with internal pull-up enabled after reset; alternates are trip-zone input 1, LIN receive (I), and SPI-B slave transmit enable (I/O).
76 GPIO13/TZ2/SPISOMIB bidirectional General-purpose I/O 13 with internal pull-up enabled after reset; alternates are trip-zone input 2 and SPI-B slave output (I/O).
77 GPIO14/TZ3/LINTXA/SPICLKB bidirectional General-purpose I/O 14 with internal pull-up enabled after reset; alternates are trip-zone input 3, LIN transmit (O), and SPI-B clock (I/O).
78 GPIO20/EQEP1A/COMP1OUT bidirectional General-purpose I/O 20 with internal pull-up enabled after reset; alternates are EQEP1A input (I) and comparator 1 direct output (O).
79 GPIO21/EQEP1B/COMP2OUT bidirectional General-purpose I/O 21 with internal pull-up enabled after reset; alternates are EQEP1B input (I) and comparator 2 direct output (O).
80 GPIO24/ECAP1/SPISIMOB bidirectional General-purpose I/O 24 with internal pull-up enabled after reset; alternates are ECAP1 (I/O) and SPI-B slave input (I/O).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-80(12x12)
Category Embedded Processors & Controllers
Pins 80

CAD (KiCad official)

  • Symbol: TMS320F28032PNT
  • Footprint: Package_QFP:LQFP-80_12x12mm_P0.5mm
  • 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)
  • 3D model files: tms320f28032pnt-etched.step / tms320f28032pnt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f28032pnt.step / tms320f28032pnt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (176 pp, sha256 cb9ccecfd6b5c484, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF