component
TMS320F28032PAGQ
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TMS320F28032PAGQ
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · TQFP-64(10x10)
TMS320F28032PAGQ from Texas Instruments, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GPIO22/EQEP1S/LINTXA | bidirectional | GPIO22 (alternates: EQEP1 strobe I/O, LIN transmit output); internal pull-up is enabled after reset and inputs are not 5 V tolerant. |
| 2 | GPIO32/SDAA/EPWMSYNCI/ADCSOCAO | bidirectional | GPIO32 (alternates: I2C-A data open-drain I/O, ePWM external sync input, ADC SOC-A output); inputs are not 5 V tolerant. |
| 3 | GPIO33/SCLA/EPWMSYNCO/ADCSOCBO | bidirectional | GPIO33 (alternates: I2C-A clock open-drain I/O, ePWM external sync output, ADC SOC-B output); inputs are not 5 V tolerant. |
| 4 | GPIO23/EQEP1I/LINRXA | bidirectional | GPIO23 (alternates: EQEP1 index I/O, LIN receive input); inputs are not 5 V tolerant. |
| 5 | VDD | power_in | CPU and logic digital supply; with the internal VREG enabled a 1.2 µF (minimum) capacitor is required at each VDD pin, and an external 1.71 V to 1.995 V supply is used only when the VREG is disabled. |
| 6 | VSS | power_in | Digital ground pin. |
| 7 | XRS | bidirectional | Device reset input and watchdog reset output, open-drain with internal pull-up; a 2.2 kΩ to 10 kΩ resistor between XRS and VDDIO is required and any external noise filter capacitor should be 100 nF or less. |
| 8 | TRST | input | JTAG test reset with internal pull-down that must be held low during normal device operation, with an external pull-up (typically 2.2 kΩ) recommended. |
| 9 | ADCINA7 | input | ADC group A channel 7 analog input with a 0 V to 3.3 V full-scale range when using the internal reference. |
| 10 | ADCINA6/COMP3A/AIO6 | input | ADC group A channel 6 analog input, also comparator 3A input and digital AIO6 (AIO pins have no internal pull-up). |
| 11 | ADCINA4/COMP2A/AIO4 | input | ADC group A channel 4 analog input, also comparator 2A input and digital AIO4 (AIO pins have no internal pull-up). |
| 12 | ADCINA3 | input | ADC group A channel 3 analog input with a 0 V to 3.3 V full-scale range when using the internal reference. |
| 13 | ADCINA2/COMP1A/AIO2 | input | ADC group A channel 2 analog input, also comparator 1A input and digital AIO2 (AIO pins have no internal pull-up). |
| 14 | ADCINA1 | input | ADC group A channel 1 analog input with a 0 V to 3.3 V full-scale range when using the internal reference. |
| 15 | ADCINA0/VREFHI | input | ADC group A channel 0 input shared with the external ADC reference high VREFHI; the two functions cannot be used at the same time and VREFHI must not exceed VDDA. |
| 16 | VDDA | power_in | Analog supply, 2.97 V to 3.63 V, with a 2.2 µF (typical) capacitor placed near this pin. |
| 17 | VSSA/VREFLO | power_in | Analog ground, which also serves as the ADC external reference low VREFLO; VREFLO is tied to VSSA internally on the 64-pin PAG package. |
| 18 | ADCINB0 | input | ADC group B channel 0 analog input with a 0 V to 3.3 V full-scale range when using the internal reference. |
| 19 | ADCINB1 | input | ADC group B channel 1 analog input with a 0 V to 3.3 V full-scale range when using the internal reference. |
| 20 | ADCINB2/COMP1B/AIO10 | input | ADC group B channel 2 analog input, also comparator 1B input and digital AIO10 (AIO pins have no internal pull-up). |
| 21 | ADCINB3 | input | ADC group B channel 3 analog input with a 0 V to 3.3 V full-scale range when using the internal reference. |
| 22 | ADCINB4/COMP2B/AIO12 | input | ADC group B channel 4 analog input, also comparator 2B input and digital AIO12 (AIO pins have no internal pull-up). |
| 23 | ADCINB6/COMP3B/AIO14 | input | ADC group B channel 6 analog input, also comparator 3B input and digital AIO14 (AIO pins have no internal pull-up). |
| 24 | ADCINB7 | input | ADC group B channel 7 analog input with a 0 V to 3.3 V full-scale range when using the internal reference. |
| 25 | GPIO31/CANTXA | bidirectional | GPIO31 (alternate: CAN-A transmit output); inputs are not 5 V tolerant. |
| 26 | GPIO30/CANRXA | bidirectional | GPIO30 (alternate: CAN-A receive input); inputs are not 5 V tolerant. |
| 27 | GPIO29/SCITXDA/SCLA/TZ3 | bidirectional | GPIO29 (alternates: SCI transmit output, I2C-A clock open-drain I/O, trip-zone 3 input); inputs are not 5 V tolerant. |
| 28 | VSS | power_in | Digital ground pin. |
| 29 | VDDIO | power_in | Digital I/O buffer and flash supply, 2.97 V to 3.63 V, with a decoupling capacitor placed on this pin. |
| 30 | TEST2 | bidirectional | Reserved for TI testing; this pin must be left unconnected. |
| 31 | GPIO9/EPWM5B/LINTXA/HRCAP1 | bidirectional | GPIO9 (alternates: ePWM5B output, LIN transmit output, high-resolution capture input 1); inputs are not 5 V tolerant. |
| 32 | GPIO28/SCIRXDA/SDAA/TZ2 | bidirectional | GPIO28 (alternates: SCI receive input, I2C-A data open-drain I/O, trip-zone 2 input); inputs are not 5 V tolerant. |
| 33 | GPIO18/SPICLKA/LINTXA/XCLKOUT | bidirectional | GPIO18 (alternates: SPI-A clock I/O, LIN transmit output, XCLKOUT output); reset default is GPIO input. |
| 34 | GPIO17/SPISOMIA/TZ3 | bidirectional | GPIO17 (alternates: SPI-A slave output/master input, trip-zone 3 input); inputs are not 5 V tolerant. |
| 35 | GPIO8/EPWM5A/ADCSOCAO | bidirectional | GPIO8 (alternates: ePWM5A output with HRPWM channel, ADC SOC-A output); inputs are not 5 V tolerant. |
| 36 | GPIO16/SPISIMOA/TZ2 | bidirectional | GPIO16 (alternates: SPI-A slave input/master output, trip-zone 2 input); inputs are not 5 V tolerant. |
| 37 | GPIO12/TZ1/SCITXDA | bidirectional | GPIO12 (alternates: trip-zone 1 input, SCI transmit output); the SPI-B alternate is not available on the PAG package. |
| 38 | GPIO7/EPWM4B/SCIRXDA | bidirectional | GPIO7 (alternates: ePWM4B output, SCI receive input); inputs are not 5 V tolerant. |
| 39 | GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO | bidirectional | GPIO6 (alternates: ePWM4A output with HRPWM channel, external ePWM sync input and output); inputs are not 5 V tolerant. |
| 40 | X2 | output | On-chip crystal oscillator output that must be connected to a crystal or ceramic resonator across X1/X2, or left unconnected if unused. |
| 41 | X1 | input | 1.8 V on-chip crystal oscillator input that must never be driven with a 3.3 V signal; connect to GND if unused. |
| 42 | VSS | power_in | Digital ground pin. |
| 43 | VDD | power_in | CPU and logic digital supply; requires a 1.2 µF (minimum) capacitor to ground at each VDD pin when the internal VREG is used. |
| 44 | GPIO19/XCLKIN/SPISTEA/LINRXA/ECAP1 | bidirectional | GPIO19 (alternates: external oscillator clock input XCLKIN, SPI-A slave transmit enable, LIN receive input, eCAP1); can produce power-up glitch pulses when the internal VREG is used. |
| 45 | GPIO38/TCK/XCLKIN | bidirectional | GPIO38 (alternates: JTAG test clock input with internal pull-up, external oscillator input XCLKIN); the TCK function must not conflict with an external clock during JTAG debug. |
| 46 | GPIO37/TDO | tri_state | GPIO37 (alternate: JTAG test data output, 8 mA drive); it also participates in boot-mode selection. |
| 47 | GPIO35/TDI | bidirectional | GPIO35 (alternate: JTAG test data input with internal pull-up). |
| 48 | GPIO36/TMS | bidirectional | GPIO36 (alternate: JTAG test mode select input with internal pull-up). |
| 49 | GPIO11/EPWM6B/LINRXA/HRCAP2 | bidirectional | GPIO11 (alternates: ePWM6B output, LIN receive input, high-resolution capture input 2); inputs are not 5 V tolerant. |
| 50 | GPIO5/EPWM3B/SPISIMOA/ECAP1 | bidirectional | GPIO5 (alternates: ePWM3B output, SPI-A slave input/master output, eCAP1 I/O); inputs are not 5 V tolerant. |
| 51 | GPIO4/EPWM3A | bidirectional | GPIO4 (alternate: ePWM3A output with HRPWM channel); inputs are not 5 V tolerant. |
| 52 | GPIO10/EPWM6A/ADCSOCBO | bidirectional | GPIO10 (alternates: ePWM6A output with HRPWM channel, ADC SOC-B output); inputs are not 5 V tolerant. |
| 53 | GPIO3/EPWM2B/SPISOMIA/COMP2OUT | bidirectional | GPIO3 (alternates: ePWM2B output, SPI-A slave output/master input, comparator 2 direct output); inputs are not 5 V tolerant. |
| 54 | GPIO2/EPWM2A | bidirectional | GPIO2 (alternate: ePWM2A output with HRPWM channel); inputs are not 5 V tolerant. |
| 55 | GPIO1/EPWM1B/COMP1OUT | bidirectional | GPIO1 (alternates: ePWM1B output, comparator 1 direct output); inputs are not 5 V tolerant. |
| 56 | GPIO0/EPWM1A | bidirectional | GPIO0 (alternate: ePWM1A output with HRPWM channel); internal pull-up is disabled at reset for PWM pins. |
| 57 | VDDIO | power_in | Digital I/O buffer and flash supply, 2.97 V to 3.63 V, with a decoupling capacitor placed on this pin. |
| 58 | VSS | power_in | Digital ground pin. |
| 59 | VDD | power_in | CPU and logic digital supply; requires a 1.2 µF (minimum) capacitor to ground at each VDD pin when the internal VREG is used. |
| 60 | VREGENZ | input | Internal regulator enable with internal pull-down: tie to VSS to enable the internal 1.8 V VREG, or to VDDIO to disable it and supply VDD externally. |
| 61 | GPIO34/COMP2OUT/COMP3OUT | bidirectional | GPIO34 (alternates: comparator 2 direct output, comparator 3 direct output); inputs are not 5 V tolerant. |
| 62 | GPIO20/EQEP1A/COMP1OUT | bidirectional | GPIO20 (alternates: EQEP1A input, comparator 1 direct output); inputs are not 5 V tolerant. |
| 63 | GPIO21/EQEP1B/COMP2OUT | bidirectional | GPIO21 (alternates: EQEP1B input, comparator 2 direct output); inputs are not 5 V tolerant. |
| 64 | GPIO24/ECAP1 | bidirectional | GPIO24 (alternate: eCAP1 I/O); the SPI-B alternate is listed only for the PN and RSH packages and is not available on PAG. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
CAD (KiCad official)
- Symbol:
TMS320F28032PAGQ - Footprint:
Package_QFP:TQFP-64_10x10mm_P0.5mm - 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
tms320f28032pagq-etched.step/tms320f28032pagq-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tms320f28032pagq.step/tms320f28032pagq.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (176 pp, sha256
cb9ccecfd6b5c484, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TMS320F28032PAGQ
**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · TQFP-64(10x10)
TMS320F28032PAGQ from Texas Instruments, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GPIO22/EQEP1S/LINTXA | bidirectional | GPIO22 (alternates: EQEP1 strobe I/O, LIN transmit output); internal pull-up is enabled after reset and inputs are not 5 V tolerant. |
| 2 | GPIO32/SDAA/EPWMSYNCI/ADCSOCAO | bidirectional | GPIO32 (alternates: I2C-A data open-drain I/O, ePWM external sync input, ADC SOC-A output); inputs are not 5 V tolerant. |
| 3 | GPIO33/SCLA/EPWMSYNCO/ADCSOCBO | bidirectional | GPIO33 (alternates: I2C-A clock open-drain I/O, ePWM external sync output, ADC SOC-B output); inputs are not 5 V tolerant. |
| 4 | GPIO23/EQEP1I/LINRXA | bidirectional | GPIO23 (alternates: EQEP1 index I/O, LIN receive input); inputs are not 5 V tolerant. |
| 5 | VDD | power_in | CPU and logic digital supply; with the internal VREG enabled a 1.2 µF (minimum) capacitor is required at each VDD pin, and an external 1.71 V to 1.995 V supply is used only when the VREG is disabled. |
| 6 | VSS | power_in | Digital ground pin. |
| 7 | XRS | bidirectional | Device reset input and watchdog reset output, open-drain with internal pull-up; a 2.2 kΩ to 10 kΩ resistor between XRS and VDDIO is required and any external noise filter capacitor should be 100 nF or less. |
| 8 | TRST | input | JTAG test reset with internal pull-down that must be held low during normal device operation, with an external pull-up (typically 2.2 kΩ) recommended. |
| 9 | ADCINA7 | input | ADC group A channel 7 analog input with a 0 V to 3.3 V full-scale range when using the internal reference. |
| 10 | ADCINA6/COMP3A/AIO6 | input | ADC group A channel 6 analog input, also comparator 3A input and digital AIO6 (AIO pins have no internal pull-up). |
| 11 | ADCINA4/COMP2A/AIO4 | input | ADC group A channel 4 analog input, also comparator 2A input and digital AIO4 (AIO pins have no internal pull-up). |
| 12 | ADCINA3 | input | ADC group A channel 3 analog input with a 0 V to 3.3 V full-scale range when using the internal reference. |
| 13 | ADCINA2/COMP1A/AIO2 | input | ADC group A channel 2 analog input, also comparator 1A input and digital AIO2 (AIO pins have no internal pull-up). |
| 14 | ADCINA1 | input | ADC group A channel 1 analog input with a 0 V to 3.3 V full-scale range when using the internal reference. |
| 15 | ADCINA0/VREFHI | input | ADC group A channel 0 input shared with the external ADC reference high VREFHI; the two functions cannot be used at the same time and VREFHI must not exceed VDDA. |
| 16 | VDDA | power_in | Analog supply, 2.97 V to 3.63 V, with a 2.2 µF (typical) capacitor placed near this pin. |
| 17 | VSSA/VREFLO | power_in | Analog ground, which also serves as the ADC external reference low VREFLO; VREFLO is tied to VSSA internally on the 64-pin PAG package. |
| 18 | ADCINB0 | input | ADC group B channel 0 analog input with a 0 V to 3.3 V full-scale range when using the internal reference. |
| 19 | ADCINB1 | input | ADC group B channel 1 analog input with a 0 V to 3.3 V full-scale range when using the internal reference. |
| 20 | ADCINB2/COMP1B/AIO10 | input | ADC group B channel 2 analog input, also comparator 1B input and digital AIO10 (AIO pins have no internal pull-up). |
| 21 | ADCINB3 | input | ADC group B channel 3 analog input with a 0 V to 3.3 V full-scale range when using the internal reference. |
| 22 | ADCINB4/COMP2B/AIO12 | input | ADC group B channel 4 analog input, also comparator 2B input and digital AIO12 (AIO pins have no internal pull-up). |
| 23 | ADCINB6/COMP3B/AIO14 | input | ADC group B channel 6 analog input, also comparator 3B input and digital AIO14 (AIO pins have no internal pull-up). |
| 24 | ADCINB7 | input | ADC group B channel 7 analog input with a 0 V to 3.3 V full-scale range when using the internal reference. |
| 25 | GPIO31/CANTXA | bidirectional | GPIO31 (alternate: CAN-A transmit output); inputs are not 5 V tolerant. |
| 26 | GPIO30/CANRXA | bidirectional | GPIO30 (alternate: CAN-A receive input); inputs are not 5 V tolerant. |
| 27 | GPIO29/SCITXDA/SCLA/TZ3 | bidirectional | GPIO29 (alternates: SCI transmit output, I2C-A clock open-drain I/O, trip-zone 3 input); inputs are not 5 V tolerant. |
| 28 | VSS | power_in | Digital ground pin. |
| 29 | VDDIO | power_in | Digital I/O buffer and flash supply, 2.97 V to 3.63 V, with a decoupling capacitor placed on this pin. |
| 30 | TEST2 | bidirectional | Reserved for TI testing; this pin must be left unconnected. |
| 31 | GPIO9/EPWM5B/LINTXA/HRCAP1 | bidirectional | GPIO9 (alternates: ePWM5B output, LIN transmit output, high-resolution capture input 1); inputs are not 5 V tolerant. |
| 32 | GPIO28/SCIRXDA/SDAA/TZ2 | bidirectional | GPIO28 (alternates: SCI receive input, I2C-A data open-drain I/O, trip-zone 2 input); inputs are not 5 V tolerant. |
| 33 | GPIO18/SPICLKA/LINTXA/XCLKOUT | bidirectional | GPIO18 (alternates: SPI-A clock I/O, LIN transmit output, XCLKOUT output); reset default is GPIO input. |
| 34 | GPIO17/SPISOMIA/TZ3 | bidirectional | GPIO17 (alternates: SPI-A slave output/master input, trip-zone 3 input); inputs are not 5 V tolerant. |
| 35 | GPIO8/EPWM5A/ADCSOCAO | bidirectional | GPIO8 (alternates: ePWM5A output with HRPWM channel, ADC SOC-A output); inputs are not 5 V tolerant. |
| 36 | GPIO16/SPISIMOA/TZ2 | bidirectional | GPIO16 (alternates: SPI-A slave input/master output, trip-zone 2 input); inputs are not 5 V tolerant. |
| 37 | GPIO12/TZ1/SCITXDA | bidirectional | GPIO12 (alternates: trip-zone 1 input, SCI transmit output); the SPI-B alternate is not available on the PAG package. |
| 38 | GPIO7/EPWM4B/SCIRXDA | bidirectional | GPIO7 (alternates: ePWM4B output, SCI receive input); inputs are not 5 V tolerant. |
| 39 | GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO | bidirectional | GPIO6 (alternates: ePWM4A output with HRPWM channel, external ePWM sync input and output); inputs are not 5 V tolerant. |
| 40 | X2 | output | On-chip crystal oscillator output that must be connected to a crystal or ceramic resonator across X1/X2, or left unconnected if unused. |
| 41 | X1 | input | 1.8 V on-chip crystal oscillator input that must never be driven with a 3.3 V signal; connect to GND if unused. |
| 42 | VSS | power_in | Digital ground pin. |
| 43 | VDD | power_in | CPU and logic digital supply; requires a 1.2 µF (minimum) capacitor to ground at each VDD pin when the internal VREG is used. |
| 44 | GPIO19/XCLKIN/SPISTEA/LINRXA/ECAP1 | bidirectional | GPIO19 (alternates: external oscillator clock input XCLKIN, SPI-A slave transmit enable, LIN receive input, eCAP1); can produce power-up glitch pulses when the internal VREG is used. |
| 45 | GPIO38/TCK/XCLKIN | bidirectional | GPIO38 (alternates: JTAG test clock input with internal pull-up, external oscillator input XCLKIN); the TCK function must not conflict with an external clock during JTAG debug. |
| 46 | GPIO37/TDO | tri_state | GPIO37 (alternate: JTAG test data output, 8 mA drive); it also participates in boot-mode selection. |
| 47 | GPIO35/TDI | bidirectional | GPIO35 (alternate: JTAG test data input with internal pull-up). |
| 48 | GPIO36/TMS | bidirectional | GPIO36 (alternate: JTAG test mode select input with internal pull-up). |
| 49 | GPIO11/EPWM6B/LINRXA/HRCAP2 | bidirectional | GPIO11 (alternates: ePWM6B output, LIN receive input, high-resolution capture input 2); inputs are not 5 V tolerant. |
| 50 | GPIO5/EPWM3B/SPISIMOA/ECAP1 | bidirectional | GPIO5 (alternates: ePWM3B output, SPI-A slave input/master output, eCAP1 I/O); inputs are not 5 V tolerant. |
| 51 | GPIO4/EPWM3A | bidirectional | GPIO4 (alternate: ePWM3A output with HRPWM channel); inputs are not 5 V tolerant. |
| 52 | GPIO10/EPWM6A/ADCSOCBO | bidirectional | GPIO10 (alternates: ePWM6A output with HRPWM channel, ADC SOC-B output); inputs are not 5 V tolerant. |
| 53 | GPIO3/EPWM2B/SPISOMIA/COMP2OUT | bidirectional | GPIO3 (alternates: ePWM2B output, SPI-A slave output/master input, comparator 2 direct output); inputs are not 5 V tolerant. |
| 54 | GPIO2/EPWM2A | bidirectional | GPIO2 (alternate: ePWM2A output with HRPWM channel); inputs are not 5 V tolerant. |
| 55 | GPIO1/EPWM1B/COMP1OUT | bidirectional | GPIO1 (alternates: ePWM1B output, comparator 1 direct output); inputs are not 5 V tolerant. |
| 56 | GPIO0/EPWM1A | bidirectional | GPIO0 (alternate: ePWM1A output with HRPWM channel); internal pull-up is disabled at reset for PWM pins. |
| 57 | VDDIO | power_in | Digital I/O buffer and flash supply, 2.97 V to 3.63 V, with a decoupling capacitor placed on this pin. |
| 58 | VSS | power_in | Digital ground pin. |
| 59 | VDD | power_in | CPU and logic digital supply; requires a 1.2 µF (minimum) capacitor to ground at each VDD pin when the internal VREG is used. |
| 60 | VREGENZ | input | Internal regulator enable with internal pull-down: tie to VSS to enable the internal 1.8 V VREG, or to VDDIO to disable it and supply VDD externally. |
| 61 | GPIO34/COMP2OUT/COMP3OUT | bidirectional | GPIO34 (alternates: comparator 2 direct output, comparator 3 direct output); inputs are not 5 V tolerant. |
| 62 | GPIO20/EQEP1A/COMP1OUT | bidirectional | GPIO20 (alternates: EQEP1A input, comparator 1 direct output); inputs are not 5 V tolerant. |
| 63 | GPIO21/EQEP1B/COMP2OUT | bidirectional | GPIO21 (alternates: EQEP1B input, comparator 2 direct output); inputs are not 5 V tolerant. |
| 64 | GPIO24/ECAP1 | bidirectional | GPIO24 (alternate: eCAP1 I/O); the SPI-B alternate is listed only for the PN and RSH packages and is not available on PAG. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
## CAD (KiCad official)
- Symbol: `TMS320F28032PAGQ`
- Footprint: `Package_QFP:TQFP-64_10x10mm_P0.5mm`
- 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `tms320f28032pagq-etched.step` / `tms320f28032pagq-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tms320f28032pagq.step` / `tms320f28032pagq.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tms320f28033) (176 pp, sha256 `cb9ccecfd6b5c484`, retrieved 2026-10-08, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tms320f28032pagq-datasheet.pdf)