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TMS320F28030PNT

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TMS320F28030PNT

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)

TMS320F28030PNT from Texas Instruments, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO22/EQEP1S/LINTXA bidirectional General-purpose I/O 22 (default GPIO function at reset) with alternates EQEP1S strobe I/O and LINTXA output; the input is not 5 V tolerant.
2 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO bidirectional General-purpose I/O 32 (default GPIO function at reset) with alternates I2C-A data (open-drain I/OD), EPWM sync input and ADC SOC-A output; the input is not 5 V tolerant.
3 GPIO33/SCLA/EPWMSYNCO/ADCSOCBO bidirectional General-purpose I/O 33 (default GPIO function at reset) with alternates I2C-A clock (open-drain I/OD), EPWM sync output and ADC SOC-B output; the input is not 5 V tolerant.
4 GPIO23/EQEP1I/LINRXA bidirectional General-purpose I/O 23 (default GPIO function at reset) with alternates EQEP1 index I/O and LIN receive input; the input is not 5 V tolerant.
5 GPIO42/COMP1OUT bidirectional General-purpose I/O 42 (default GPIO function at reset) with alternate direct comparator 1 output COMP1OUT; the input is not 5 V tolerant.
6 GPIO43/COMP2OUT bidirectional General-purpose I/O 43 (default GPIO function at reset) with alternate direct comparator 2 output COMP2OUT; the input is not 5 V tolerant.
7 VDD power_in CPU and logic digital supply; with the internal VREG used a 1.2 µF (minimum) capacitor is required on each VDD pin, and with VREG disabled it is supplied externally at 1.71 V to 1.995 V (1.8 V nominal).
8 VSS power_in Digital ground pin.
9 XRS bidirectional Device reset input and watchdog reset output, an open-drain pin with internal pull-up; a 2.2 kΩ to 10 kΩ resistor to VDDIO is required and any noise filter capacitor to VSS must be 100 nF or less.
10 TRST input JTAG test reset with internal pull-down, active high, which must be held low during normal operation and typically needs an external pull-up of about 2.2 kΩ.
11 ADCINA7 input ADC group A channel 7 analog input.
12 ADCINA6/COMP3A/AIO6 input ADC group A channel 6 analog input, also comparator 3A input and digital AIO6 (AIO6 is I/O when AIO function is enabled).
13 ADCINA5 input ADC group A channel 5 analog input.
14 ADCINA4/COMP2A/AIO4 input ADC group A channel 4 analog input, also comparator 2A input and digital AIO4.
15 ADCINA3 input ADC group A channel 3 analog input.
16 ADCINA2/COMP1A/AIO2 input ADC group A channel 2 analog input, also comparator 1A input and digital AIO2.
17 ADCINA1 input ADC group A channel 1 analog input.
18 ADCINA0 input ADC group A channel 0 analog input; on the PN package this is a separate pin from VREFHI (pin 19).
19 VREFHI input ADC external reference high, used only in external reference mode, and must not exceed VDDA.
20 VDDA power_in Analog supply, 2.97 V to 3.63 V (3.3 V nominal), with a 2.2 µF (typical) capacitor placed near this pin.
21 VSSA power_in Analog ground pin.
22 VREFLO input ADC external reference low; on the PN package this is a separate pin, while it is tied to VSSA on the PAG and RSH packages.
23 ADCINB0 input ADC group B channel 0 analog input.
24 ADCINB1 input ADC group B channel 1 analog input.
25 ADCINB2/COMP1B/AIO10 input ADC group B channel 2 analog input, also comparator 1B input and digital AIO10.
26 ADCINB3 input ADC group B channel 3 analog input.
27 ADCINB4/COMP2B/AIO12 input ADC group B channel 4 analog input, also comparator 2B input and digital AIO12.
28 ADCINB5 input ADC group B channel 5 analog input (available on the PN package only).
29 ADCINB6/COMP3B/AIO14 input ADC group B channel 6 analog input, also comparator 3B input and digital AIO14.
30 ADCINB7 input ADC group B channel 7 analog input.
31 GPIO27/HRCAP2/SPISTEB bidirectional General-purpose I/O 27 (default GPIO function at reset) with alternates HRCAP2 input and SPI-B slave transmit enable I/O; the input is not 5 V tolerant.
32 GPIO31/CANTXA bidirectional General-purpose I/O 31 (default GPIO function at reset) with alternate eCAN-A transmit output CANTXA; the input is not 5 V tolerant.
33 GPIO30/CANRXA bidirectional General-purpose I/O 30 (default GPIO function at reset) with alternate eCAN-A receive input CANRXA; the input is not 5 V tolerant.
34 GPIO29/SCITXDA/SCLA/TZ3 bidirectional General-purpose I/O 29 (default GPIO function at reset) with alternates SCI-A transmit output, I2C-A clock (open-drain I/OD) and trip-zone input TZ3; the input is not 5 V tolerant.
35 VSS power_in Digital ground pin.
36 VDDIO power_in Digital I/O buffer and flash supply, 2.97 V to 3.63 V (3.3 V nominal), with a decoupling capacitor on each VDDIO pin; a single supply is used when VREG is enabled.
37 GPIO26/HRCAP1/SPICLKB bidirectional General-purpose I/O 26 (default GPIO function at reset) with alternates HRCAP1 input and SPI-B clock I/O; the input is not 5 V tolerant.
38 TEST2 unconnected Reserved for TI test use; must be left unconnected.
39 GPIO9/EPWM5B/LINTXA/HRCAP1 bidirectional General-purpose I/O 9 (default GPIO function at reset) with alternates EPWM5B output, LIN transmit output and HRCAP1 input; PWM pin pull-ups are disabled at reset and the input is not 5 V tolerant.
40 GPIO28/SCIRXDA/SDAA/TZ2 bidirectional General-purpose I/O 28 (default GPIO function at reset) with alternates SCI-A receive input, I2C-A data (open-drain I/OD) and trip-zone input TZ2; the input is not 5 V tolerant.
41 GPIO18/SPICLKA/LINTXA/XCLKOUT bidirectional General-purpose I/O 18 with alternates SPI-A clock I/O, LIN transmit output and XCLKOUT output (XCLKOUT is SYSCLKOUT/4 at reset); this pin is in Output Group 2 with 8 mA source/sink limits.
42 GPIO17/SPISOMIA/TZ3 bidirectional General-purpose I/O 17 (default GPIO function at reset) with alternates SPI-A slave-out/master-in I/O and trip-zone input TZ3; this pin is in Output Group 2.
43 GPIO8/EPWM5A/ADCSOCAO bidirectional General-purpose I/O 8 (default GPIO function at reset) with alternates EPWM5A output and ADC SOC-A output; PWM pin pull-ups are disabled at reset.
44 GPIO25/SPISOMIB bidirectional General-purpose I/O 25 (default GPIO function at reset) with alternate SPI-B slave-out/master-in I/O, available on the PN and RSH packages only.
45 GPIO44 bidirectional General-purpose I/O 44 (default GPIO function at reset) with no alternate peripheral function listed.
46 GPIO16/SPISIMOA/TZ2 bidirectional General-purpose I/O 16 with alternates SPI-A slave-in/master-out I/O and trip-zone input TZ2; this pin is in Output Group 2.
47 GPIO12/TZ1/SCITXDA/SPISIMOB bidirectional General-purpose I/O 12 (default GPIO function at reset) with alternates trip-zone input TZ1, SCI-A transmit output and SPI-B slave-in/master-out I/O (SPI-B is available on the PN package only).
48 GPIO41/EPWM7B bidirectional General-purpose I/O 41 (default GPIO function at reset) with alternate EPWM7B output; PWM pin pull-ups are disabled at reset.
49 GPIO7/EPWM4B/SCIRXDA bidirectional General-purpose I/O 7 (default GPIO function at reset) with alternates EPWM4B output and SCI-A receive input; PWM pin pull-ups are disabled at reset.
50 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO bidirectional General-purpose I/O 6 (default GPIO function at reset) with alternates EPWM4A output (also HRPWM channel), external ePWM sync input and external ePWM sync output.
51 X2 output On-chip crystal oscillator output; a crystal or ceramic resonator is connected between X1 and X2, and X2 must be left unconnected if not used.
52 X1 input 1.8 V on-chip crystal oscillator input that must never be driven with a 3.3 V level and must be tied to GND if not used.
53 VSS power_in Digital ground pin.
54 VDD power_in CPU and logic digital supply pin; a 1.2 µF (minimum) capacitor to ground is required on each VDD pin when the internal VREG is used.
55 GPIO19/XCLKIN/SPISTEA/LINRXA/ECAP1 bidirectional General-purpose I/O 19 with alternates external oscillator input XCLKIN, SPI-A slave transmit enable I/O, LIN receive input and ECAP1 I/O; it is subject to a power-up glitch when the internal VREG is used.
56 GPIO39 bidirectional General-purpose I/O 39 with no alternate peripheral function listed.
57 GPIO38/TCK/XCLKIN bidirectional General-purpose I/O 38 (default GPIO function at reset) with alternates JTAG test clock TCK (internal pull-up) and external oscillator input XCLKIN.
58 GPIO37/TDO bidirectional General-purpose I/O 37 with alternate JTAG test data output TDO (O/Z, 8 mA drive); it is subject to a power-up glitch when the internal VREG is used.
59 GPIO35/TDI bidirectional General-purpose I/O 35 with alternate JTAG test data input TDI (internal pull-up); it is subject to a power-up glitch when the internal VREG is used.
60 GPIO36/TMS bidirectional General-purpose I/O 36 with alternate JTAG test mode select TMS (internal pull-up); it is subject to a power-up glitch when the internal VREG is used.
61 GPIO11/EPWM6B/LINRXA/HRCAP2 bidirectional General-purpose I/O 11 (default GPIO function at reset) with alternates EPWM6B output, LIN receive input and HRCAP2 input; PWM pin pull-ups are disabled at reset.
62 GPIO5/EPWM3B/SPISIMOA/ECAP1 bidirectional General-purpose I/O 5 (default GPIO function at reset) with alternates EPWM3B output, SPI-A slave-in/master-out I/O and ECAP1 I/O.
63 GPIO4/EPWM3A bidirectional General-purpose I/O 4 (default GPIO function at reset) with alternate EPWM3A output (also HRPWM channel); PWM pin pull-ups are disabled at reset.
64 GPIO40/EPWM7A bidirectional General-purpose I/O 40 (default GPIO function at reset) with alternate EPWM7A output (also HRPWM channel).
65 GPIO10/EPWM6A/ADCSOCBO bidirectional General-purpose I/O 10 (default GPIO function at reset) with alternates EPWM6A output (also HRPWM channel) and ADC SOC-B output.
66 GPIO3/EPWM2B/SPISOMIA/COMP2OUT bidirectional General-purpose I/O 3 (default GPIO function at reset) with alternates EPWM2B output, SPI-A slave-out/master-in I/O and direct comparator 2 output COMP2OUT.
67 GPIO2/EPWM2A bidirectional General-purpose I/O 2 (default GPIO function at reset) with alternate EPWM2A output (also HRPWM channel); PWM pin pull-ups are disabled at reset.
68 GPIO1/EPWM1B/COMP1OUT bidirectional General-purpose I/O 1 (default GPIO function at reset) with alternates EPWM1B output and direct comparator 1 output COMP1OUT.
69 GPIO0/EPWM1A bidirectional General-purpose I/O 0 (default GPIO function at reset) with alternate EPWM1A output (also HRPWM channel); PWM pin pull-ups are disabled at reset.
70 VDDIO power_in Digital I/O buffer and flash supply pin, 2.97 V to 3.63 V, with a decoupling capacitor on each VDDIO pin.
71 VSS power_in Digital ground pin.
72 VDD power_in CPU and logic digital supply pin; a 1.2 µF (minimum) capacitor to ground is required on each VDD pin when the internal VREG is used.
73 VREGENZ input Internal voltage regulator enable with internal pull-down: tie to VSS to enable the internal 1.8 V VREG, or to VDDIO to disable it and use an external 1.8 V supply.
74 GPIO34/COMP2OUT/COMP3OUT bidirectional General-purpose I/O 34 (default GPIO function at reset) with alternates direct comparator 2 output and comparator 3 output COMP3OUT; it is subject to a power-up glitch when the internal VREG is used and is a boot-mode pin.
75 GPIO15/TZ1/LINRXA/SPISTEB bidirectional General-purpose I/O 15 with alternates trip-zone input TZ1, LIN receive input and SPI-B slave transmit enable I/O.
76 GPIO13/TZ2/SPISOMIB bidirectional General-purpose I/O 13 (default GPIO function at reset) with alternates trip-zone input TZ2 and SPI-B slave-out/master-in I/O.
77 GPIO14/TZ3/LINTXA/SPICLKB bidirectional General-purpose I/O 14 (default GPIO function at reset) with alternates trip-zone input TZ3, LIN transmit output and SPI-B clock I/O.
78 GPIO20/EQEP1A/COMP1OUT bidirectional General-purpose I/O 20 (default GPIO function at reset) with alternates EQEP1A input and direct comparator 1 output COMP1OUT.
79 GPIO21/EQEP1B/COMP2OUT bidirectional General-purpose I/O 21 (default GPIO function at reset) with alternates EQEP1B input and direct comparator 2 output COMP2OUT.
80 GPIO24/ECAP1/SPISIMOB bidirectional General-purpose I/O 24 (default GPIO function at reset) with alternates ECAP1 I/O and SPI-B slave-in/master-out I/O, available on the PN and RSH packages only.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-80(12x12)
Category Embedded Processors & Controllers
Pins 80

CAD (KiCad official)

  • Symbol: TMS320F28030PNT
  • Footprint: Package_QFP:LQFP-80_12x12mm_P0.5mm
  • 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)
  • 3D model files: tms320f28030pnt-etched.step / tms320f28030pnt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f28030pnt.step / tms320f28030pnt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (176 pp, sha256 cb9ccecfd6b5c484, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF