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TMS320F2802PZS

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TMS320F2802PZS

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

TMS320F2802PZS from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO12/TZ1/SPISIMOB bidirectional GPIO12 (I/O/Z, 4 mA typical, internal pullup enabled at reset) with trip-zone input TZ1 and SPI-B slave-in/master-out alternate functions.
2 VSS power_in Digital ground pin.
3 VDDIO power_in Digital I/O power pin, 3.3 V.
4 GPIO29/SCITXDA/TZ6 bidirectional GPIO29 with 8 mA (typical) output buffer; alternate functions SCI-A transmit data and trip-zone input TZ6.
5 GPIO33/SCLA/EPWMSYNCO/ADCSOCBO bidirectional GPIO33 (I/O/Z, internal pullup enabled at reset) with I2C-A clock open-drain port, ePWM sync output and ADC start-of-conversion B output.
6 GPIO30/CANRXA bidirectional GPIO30 with 8 mA (typical) output buffer; alternate function eCAN-A receive data input.
7 GPIO31/CANTXA bidirectional GPIO31 with 8 mA (typical) output buffer; alternate function eCAN-A transmit data output.
8 SPICLKB/GPIO14/TZ3 bidirectional GPIO14 (internal pullup enabled at reset) with trip-zone input TZ3 and SPI-B clock input/output.
9 SPISTEB/GPIO15/TZ4 bidirectional GPIO15 (internal pullup enabled at reset) with trip-zone input TZ4 and SPI-B slave transmit enable input/output.
10 VDD power_in CPU and logic digital power pin, 1.8 V.
11 VSS power_in Digital ground pin.
12 VDD1A18 power_in ADC analog power pin, 1.8 V.
13 VSS1AGND power_in ADC analog ground pin.
14 VSSA2 power_in ADC analog ground pin.
15 VDDA2 power_in ADC analog power pin, 3.3 V.
16 ADCINA7 input ADC Group A, channel 7 analog input, 0 to 3 V with respect to ADCLO.
17 ADCINA6 input ADC Group A, channel 6 analog input, 0 to 3 V with respect to ADCLO.
18 ADCINA5 input ADC Group A, channel 5 analog input, 0 to 3 V with respect to ADCLO.
19 ADCINA4 input ADC Group A, channel 4 analog input, 0 to 3 V with respect to ADCLO.
20 ADCINA3 input ADC Group A, channel 3 analog input, 0 to 3 V with respect to ADCLO.
21 ADCINA2 input ADC Group A, channel 2 analog input, 0 to 3 V with respect to ADCLO.
22 ADCINA1 input ADC Group A, channel 1 analog input, 0 to 3 V with respect to ADCLO.
23 ADCINA0 input ADC Group A, channel 0 analog input, 0 to 3 V with respect to ADCLO.
24 ADCLO input ADC low reference; connect to analog ground.
25 VSSAIO power_in ADC analog I/O ground pin.
26 VDDAIO power_in ADC analog I/O power pin, 3.3 V.
27 ADCINB0 input ADC Group B, channel 0 analog input, 0 to 3 V with respect to ADCLO.
28 ADCINB1 input ADC Group B, channel 1 analog input, 0 to 3 V with respect to ADCLO.
29 ADCINB2 input ADC Group B, channel 2 analog input, 0 to 3 V with respect to ADCLO.
30 ADCINB3 input ADC Group B, channel 3 analog input, 0 to 3 V with respect to ADCLO.
31 ADCINB4 input ADC Group B, channel 4 analog input, 0 to 3 V with respect to ADCLO.
32 ADCINB5 input ADC Group B, channel 5 analog input, 0 to 3 V with respect to ADCLO.
33 ADCINB6 input ADC Group B, channel 6 analog input, 0 to 3 V with respect to ADCLO.
34 ADCINB7 input ADC Group B, channel 7 analog input, 0 to 3 V with respect to ADCLO.
35 ADCREFIN input External ADC reference input, used only when an external reference is selected.
36 ADCREFM output Internal reference medium output; requires a 2.2 µF ceramic bypass capacitor with ESR under 1.5 Ω to analog ground and must not be loaded by external circuitry.
37 ADCREFP output Internal reference positive output; requires a 2.2 µF ceramic bypass capacitor with ESR under 1.5 Ω to analog ground and must not be loaded by external circuitry.
38 ADCRESEXT passive ADC external current bias resistor; connect a 22 kΩ resistor to analog ground.
39 VSS2AGND power_in ADC analog ground pin.
40 VDD2A18 power_in ADC analog power pin, 1.8 V.
41 VSS power_in Digital ground pin.
42 VDD power_in CPU and logic digital power pin, 1.8 V.
43 GPIO34 bidirectional General-purpose I/O 34 (I/O/Z, 4 mA typical, internal pullup enabled at reset) with no peripheral alternate function listed.
44 GPIO1/EPWM1B bidirectional General-purpose I/O 1 (I/O/Z, internal pullup not enabled at reset) with ePWM1 output B alternate function.
45 GPIO2/EPWM2A bidirectional General-purpose I/O 2 (I/O/Z, internal pullup not enabled at reset) with ePWM2 output A and HRPWM channel alternate function.
46 VDDIO power_in Digital I/O power pin, 3.3 V.
47 GPIO0/EPWM1A bidirectional General-purpose I/O 0 (I/O/Z, internal pullup not enabled at reset) with ePWM1 output A and HRPWM channel alternate function.
48 GPIO3/EPWM2B bidirectional General-purpose I/O 3 (I/O/Z, internal pullup not enabled at reset) with ePWM2 output B alternate function.
49 VSS power_in Digital ground pin.
50 GPIO16/SPISIMOA/TZ5 bidirectional GPIO16 (I/O/Z, 4 mA typical, internal pullup enabled at reset) with SPI-A slave-in/master-out and trip-zone input TZ5 alternate functions.
51 GPIO4/EPWM3A bidirectional General-purpose I/O 4 (I/O/Z, internal pullup not enabled at reset) with ePWM3 output A and HRPWM channel alternate function.
52 GPIO17/SPISOMIA/TZ6 bidirectional GPIO17 (I/O/Z, 4 mA typical, internal pullup enabled at reset) with SPI-A slave-out/master-in and trip-zone input TZ6 alternate functions.
53 GPIO5/EPWM3B/ECAP1 bidirectional General-purpose I/O 5 (I/O/Z, internal pullup not enabled at reset) with ePWM3 output B and enhanced capture 1 alternate functions.
54 GPIO18/SPICLKA bidirectional GPIO18 (I/O/Z, 4 mA typical, internal pullup enabled at reset) with SPI-A clock input/output alternate function.
55 VSS power_in Digital ground pin.
56 GPIO6/EPWMSYNCI/EPWMSYNCO bidirectional General-purpose I/O 6 (I/O/Z, internal pullup not enabled at reset) with external ePWM sync pulse input and output alternate functions.
57 GPIO19/SPISTEA bidirectional GPIO19 (I/O/Z, 4 mA typical, internal pullup enabled at reset) with SPI-A slave transmit enable input/output alternate function.
58 GPIO7/ECAP2 bidirectional General-purpose I/O 7 (I/O/Z, internal pullup not enabled at reset) with enhanced capture 2 input/output alternate function.
59 VDD power_in CPU and logic digital power pin, 1.8 V.
60 GPIO8/ADCSOCAO bidirectional General-purpose I/O 8 (I/O/Z, internal pullup not enabled at reset) with ADC start-of-conversion A output alternate function.
61 GPIO9 bidirectional General-purpose I/O 9 (I/O/Z, internal pullup not enabled at reset); its ePWM5B, SCI-B and ECAP3 alternate functions are not available on F2802.
62 VSS power_in Digital ground pin.
63 GPIO20/EQEP1A bidirectional GPIO20 (I/O/Z, 4 mA typical, internal pullup enabled at reset) with enhanced QEP1 input A alternate function.
64 GPIO10/ADCSOCBO bidirectional General-purpose I/O 10 (I/O/Z, internal pullup not enabled at reset) with ADC start-of-conversion B output alternate function.
65 VDDIO power_in Digital I/O power pin, 3.3 V.
66 XCLKOUT tri_state Output clock derived from SYSCLKOUT at the same, half, or quarter frequency (reset value SYSCLKOUT/4, controlled by XCLKOUTDIV, 8 mA drive); not placed in high-impedance during reset.
67 GPIO21/EQEP1B bidirectional GPIO21 (I/O/Z, 4 mA typical, internal pullup enabled at reset) with enhanced QEP1 input B alternate function.
68 VDD power_in CPU and logic digital power pin, 1.8 V.
69 VSS power_in Digital ground pin.
70 GPIO11 bidirectional General-purpose I/O 11 (I/O/Z, internal pullup not enabled at reset); its EPWM6B, SCI-B and ECAP4 alternate functions are not available on F2802.
71 GPIO22/EQEP1S bidirectional GPIO22 (I/O/Z, 4 mA typical, internal pullup enabled at reset) with enhanced QEP1 strobe input/output alternate function.
72 GPIO23/EQEP1I bidirectional GPIO23 (I/O/Z, 4 mA typical, internal pullup enabled at reset) with enhanced QEP1 index input/output alternate function.
73 TDI input JTAG test data input with internal pullup, clocked into the selected register on the rising edge of TCK.
74 TMS input JTAG test-mode select with internal pullup, clocked into the TAP controller on the rising edge of TCK.
75 TCK input JTAG test clock with internal pullup.
76 TDO tri_state JTAG scan test data output, shifted out on the falling edge of TCK with 8 mA drive (O/Z).
77 VSS power_in Digital ground pin.
78 XRS bidirectional Device reset input and watchdog reset output with internal pullup; driven low for 512 OSCCLK cycles during a watchdog reset, and must be driven by an open-drain device if externally driven.
79 SPISTEB/GPIO27 bidirectional GPIO27 (I/O/Z, 4 mA typical, internal pullup enabled at reset) with SPI-B slave transmit enable input/output alternate function.
80 EMU0 bidirectional Emulator pin 0, defined as input/output through JTAG scan with an external 2.2 kΩ to 4.7 kΩ pullup recommended; with EMU0 high and EMU1 low, a rising TRST edge latches boundary-scan mode.
81 EMU1 bidirectional Emulator pin 1, defined as input/output through JTAG scan with an external 2.2 kΩ to 4.7 kΩ pullup recommended.
82 VDDIO power_in Digital I/O power pin, 3.3 V.
83 SPISIMOB/GPIO24/ECAP1 bidirectional GPIO24 (I/O/Z, 4 mA typical, internal pullup enabled at reset) with enhanced capture 1 and SPI-B slave-in/master-out alternate functions.
84 TRST input JTAG test reset with internal pulldown; must be held low during normal operation and requires an external pulldown (2.2 kΩ generally adequate), with no pullup used.
85 VDD power_in CPU and logic digital power pin, 1.8 V.
86 X2 output Internal oscillator output; a quartz crystal or ceramic resonator connects across X1 and X2, and X2 must be left unconnected if not used.
87 VSS power_in Digital ground pin.
88 X1 input Internal/external oscillator input referenced to the 1.8-V core supply, which can also take a 1.8-V external oscillator when XCLKIN is tied to ground.
89 VSS power_in Digital ground pin.
90 XCLKIN input External 3.3-V oscillator input; X1 must be tied to GND when it is used, and XCLKIN must be tied to GND when a crystal or 1.8-V oscillator on X1 is used.
91 GPIO25/ECAP2/SPISOMIB bidirectional GPIO25 (I/O/Z, 4 mA typical, internal pullup enabled at reset) with enhanced capture 2 and SPI-B master-in/slave-out alternate functions.
92 GPIO28/SCIRXDA/TZ5 bidirectional GPIO28 with 8 mA (typical) output buffer; alternate functions SCI-A receive data and trip-zone input TZ5.
93 VDD power_in CPU and logic digital power pin, 1.8 V.
94 VSS power_in Digital ground pin.
95 SPISOMIB/GPIO13/TZ2 bidirectional GPIO13 (I/O/Z, 4 mA typical, internal pullup enabled at reset) with trip-zone input TZ2 and SPI-B slave-out/master-in alternate functions.
96 VDD3VFL power_in 3.3-V flash core power pin that must be connected to 3.3 V at all times.
97 TEST1 unconnected Test pin reserved for TI; must be left unconnected.
98 TEST2 unconnected Test pin reserved for TI; must be left unconnected.
99 SPICLKB/GPIO26 bidirectional GPIO26 (I/O/Z, 4 mA typical, internal pullup enabled at reset) with SPI-B clock input/output alternate function.
100 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO bidirectional GPIO32 (I/O/Z, internal pullup enabled at reset) with I2C-A data open-drain bidirectional port, ePWM sync input and ADC start-of-conversion A output alternate functions.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: TMS320F2802PZS
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: tms320f2802pzs-etched.step / tms320f2802pzs-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f2802pzs.step / tms320f2802pzs.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (157 pp, sha256 a13113c4c002c567, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF