component
TMS320F28027PTR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TMS320F28027PTR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)
TMS320F28027PTR from Texas Instruments, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GPIO29/SCITXDA/SCLA/TZ3 | bidirectional | General-purpose I/O 29 (Group 2, 8 mA) with SCI-A transmit, I2C-A clock (open-drain) and trip-zone 3 alternate functions; inputs are not 5 V tolerant. |
| 2 | TRST | input | JTAG test reset with internal pull-down; must be held low during normal operation, needs an external pull-up (about 2.2 kΩ typical) and leaving it low runs the device in functional mode. |
| 3 | XRS | bidirectional | Open-drain device reset input and watchdog reset output with internal pull-up; a 2.2 kΩ to 10 kΩ resistor to VDDIO is required and any noise-filter capacitor to VSS must be 100 nF or less. |
| 4 | ADCINA6/AIO6 | input | ADC group A channel 6 analog input, also usable as digital AIO6; AIO pins have no internal pull-up. |
| 5 | ADCINA4/COMP2A/AIO4 | input | ADC group A channel 4 analog input, also comparator 2A input (48-pin device only) and AIO4. |
| 6 | ADCINA7 | input | ADC group A channel 7 analog input, with full-scale range of 0 V to 3.3 V (or VREFHI/VREFLO ratiometric). |
| 7 | ADCINA3 | input | ADC group A channel 3 analog input, with full-scale range of 0 V to 3.3 V (or VREFHI/VREFLO ratiometric). |
| 8 | ADCINA1 | input | ADC group A channel 1 analog input, with full-scale range of 0 V to 3.3 V (or VREFHI/VREFLO ratiometric). |
| 9 | ADCINA2/COMP1A/AIO2 | input | ADC group A channel 2 analog input, also comparator 1A input and AIO2. |
| 10 | ADCINA0/VREFHI | input | ADC group A channel 0 analog input; doubles as external ADC high reference VREFHI, used only in external reference mode and not to exceed VDDA. |
| 11 | VDDA | power_in | Analog supply, 2.97 V to 3.63 V (3.3 V nominal); place about 2.2 µF capacitor close to this pin. |
| 12 | VSSA/VREFLO | power_in | Analog ground, also the ADC external reference low VREFLO which is always tied to ground. |
| 13 | ADCINB1 | input | ADC group B channel 1 analog input, with full-scale range of 0 V to 3.3 V (or VREFHI/VREFLO ratiometric). |
| 14 | ADCINB2/COMP1B/AIO10 | input | ADC group B channel 2 analog input, also comparator 1B input and AIO10. |
| 15 | ADCINB3 | input | ADC group B channel 3 analog input, with full-scale range of 0 V to 3.3 V (or VREFHI/VREFLO ratiometric). |
| 16 | ADCINB4/COMP2B/AIO12 | input | ADC group B channel 4 analog input, also comparator 2B input (48-pin device only) and AIO12. |
| 17 | ADCINB6/AIO14 | input | ADC group B channel 6 analog input, also usable as digital AIO14. |
| 18 | ADCINB7 | input | ADC group B channel 7 analog input, with full-scale range of 0 V to 3.3 V (or VREFHI/VREFLO ratiometric). |
| 19 | GPIO34/COMP2OUT | bidirectional | General-purpose I/O 34 with comparator 2 direct output (48-pin only) and boot-mode select function; may glitch at power-up when the on-chip VREG is used. |
| 20 | GPIO35/TDI | bidirectional | General-purpose I/O 35 with JTAG test data input (TDI) on the rising edge of TCK and an internal pull-up; may glitch at power-up when the on-chip VREG is used. |
| 21 | GPIO36/TMS | bidirectional | General-purpose I/O 36 with JTAG test mode select (TMS) input to the TAP controller on TCK rising edge and an internal pull-up; Group 2 pin (8 mA). |
| 22 | GPIO37/TDO | bidirectional | General-purpose I/O 37 with JTAG test data output (TDO, 8 mA drive); also used for boot-mode selection, which is unavailable when a JTAG debug probe is connected. |
| 23 | GPIO38/XCLKIN/TCK | bidirectional | General-purpose I/O 38 with JTAG test clock (TCK, internal pull-up) and external oscillator input XCLKIN (default clock source); using it as external clock may conflict with JTAG debug. |
| 24 | GPIO18/SPICLKA/SCITXDA/XCLKOUT | bidirectional | General-purpose I/O 18 (Group 2, 8 mA) with SPI-A clock, SCI-A transmit and XCLKOUT output; XCLKOUT resets to SYSCLKOUT/4. |
| 25 | GPIO19/XCLKIN/SPISTEA/SCIRXDA/ECAP1 | bidirectional | General-purpose I/O 19 (Group 2, 8 mA) with external oscillator input XCLKIN, SPI-A slave transmit enable, SCI-A receive and eCAP1; may glitch at power-up when the on-chip VREG is used. |
| 26 | GPIO17/SPISOMIA/TZ3 | bidirectional | General-purpose I/O 17 (Group 2, 8 mA) with SPI-A slave output / master input and trip-zone 3; may glitch at power-up when the on-chip VREG is used. |
| 27 | GPIO16/SPISIMOA/TZ2 | bidirectional | General-purpose I/O 16 (Group 2, 8 mA) with SPI-A slave input / master output and trip-zone 2. |
| 28 | GPIO1/EPWM1B/COMP1OUT | bidirectional | General-purpose I/O 1 with ePWM1 output B and comparator 1 direct output. |
| 29 | GPIO0/EPWM1A | bidirectional | General-purpose I/O 0 with ePWM1 output A and HRPWM channel; GPIO0 can also feed XINT inputs. |
| 30 | TEST | unconnected | Reserved for TI; must be kept unconnected. |
| 31 | GPIO32/SDAA/EPWMSYNCI/ADCSOCAO | bidirectional | General-purpose I/O 32 with I2C-A data (open-drain), external ePWM sync input and ADC start-of-conversion A output. |
| 32 | VDD | power_in | CPU and logic digital supply; when the internal VREG is enabled a 1.2 µF (minimum) capacitor to ground is required on each VDD pin, and with VREG disabled it is supplied 1.71 V to 1.995 V (1.8 V nominal). |
| 33 | VSS | power_in | Digital ground pin. |
| 34 | VREGENZ | input | Internal regulator enable with internal pull-down; tie to VSS to enable the internal 1.8 V VREG, or tie to VDDIO to disable it and supply VDD externally. |
| 35 | VDDIO | power_in | Digital I/O and Flash supply, 2.97 V to 3.63 V (3.3 V nominal) with decoupling capacitor on this pin; single supply when VREG is enabled. |
| 36 | GPIO33/SCLA/EPWMSYNCO/ADCSOCBO | bidirectional | General-purpose I/O 33 with I2C-A clock (open-drain), external ePWM sync output and ADC start-of-conversion B output. |
| 37 | GPIO2/EPWM2A | bidirectional | General-purpose I/O 2 with ePWM2 output A and HRPWM channel. |
| 38 | GPIO3/EPWM2B/COMP2OUT | bidirectional | General-purpose I/O 3 with ePWM2 output B and comparator 2 direct output (48-pin only). |
| 39 | GPIO4/EPWM3A | bidirectional | General-purpose I/O 4 with ePWM3 output A and HRPWM channel. |
| 40 | GPIO5/EPWM3B/ECAP1 | bidirectional | General-purpose I/O 5 with ePWM3 output B and enhanced capture input/output 1 (eCAP1). |
| 41 | GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO | bidirectional | General-purpose I/O 6 with ePWM4 output A and HRPWM channel, plus external ePWM sync input and sync output. |
| 42 | GPIO7/EPWM4B/SCIRXDA | bidirectional | General-purpose I/O 7 with ePWM4 output B and SCI-A receive data input. |
| 43 | VDD | power_in | CPU and logic digital supply; when the internal VREG is enabled a 1.2 µF (minimum) capacitor to ground is required on each VDD pin. |
| 44 | VSS | power_in | Digital ground pin. |
| 45 | X1 | input | 1.8 V on-chip crystal oscillator input that must not be driven with 3.3 V signals; connect to GND if the oscillator is unused and use with X2 and a crystal or resonator when used. |
| 46 | X2 | output | On-chip crystal oscillator output; connect to X1 with a crystal or resonator, and leave unconnected if not used. |
| 47 | GPIO12/TZ1/SCITXDA | bidirectional | General-purpose I/O 12 with trip-zone 1 input and SCI-A transmit data output. |
| 48 | GPIO28/SCIRXDA/SDAA/TZ2 | bidirectional | General-purpose I/O 28 with SCI receive data input, I2C-A data (open-drain) and trip-zone 2 input. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 48 |
CAD (KiCad official)
- Symbol:
TMS320F28027PTR - Footprint:
Package_QFP:LQFP-48_7x7mm_P0.5mm - 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
tms320f28027ptr-etched.step/tms320f28027ptr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tms320f28027ptr.step/tms320f28027ptr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (147 pp, sha256
b90c388f4142c4b5, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TMS320F28027PTR
**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)
TMS320F28027PTR from Texas Instruments, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GPIO29/SCITXDA/SCLA/TZ3 | bidirectional | General-purpose I/O 29 (Group 2, 8 mA) with SCI-A transmit, I2C-A clock (open-drain) and trip-zone 3 alternate functions; inputs are not 5 V tolerant. |
| 2 | TRST | input | JTAG test reset with internal pull-down; must be held low during normal operation, needs an external pull-up (about 2.2 kΩ typical) and leaving it low runs the device in functional mode. |
| 3 | XRS | bidirectional | Open-drain device reset input and watchdog reset output with internal pull-up; a 2.2 kΩ to 10 kΩ resistor to VDDIO is required and any noise-filter capacitor to VSS must be 100 nF or less. |
| 4 | ADCINA6/AIO6 | input | ADC group A channel 6 analog input, also usable as digital AIO6; AIO pins have no internal pull-up. |
| 5 | ADCINA4/COMP2A/AIO4 | input | ADC group A channel 4 analog input, also comparator 2A input (48-pin device only) and AIO4. |
| 6 | ADCINA7 | input | ADC group A channel 7 analog input, with full-scale range of 0 V to 3.3 V (or VREFHI/VREFLO ratiometric). |
| 7 | ADCINA3 | input | ADC group A channel 3 analog input, with full-scale range of 0 V to 3.3 V (or VREFHI/VREFLO ratiometric). |
| 8 | ADCINA1 | input | ADC group A channel 1 analog input, with full-scale range of 0 V to 3.3 V (or VREFHI/VREFLO ratiometric). |
| 9 | ADCINA2/COMP1A/AIO2 | input | ADC group A channel 2 analog input, also comparator 1A input and AIO2. |
| 10 | ADCINA0/VREFHI | input | ADC group A channel 0 analog input; doubles as external ADC high reference VREFHI, used only in external reference mode and not to exceed VDDA. |
| 11 | VDDA | power_in | Analog supply, 2.97 V to 3.63 V (3.3 V nominal); place about 2.2 µF capacitor close to this pin. |
| 12 | VSSA/VREFLO | power_in | Analog ground, also the ADC external reference low VREFLO which is always tied to ground. |
| 13 | ADCINB1 | input | ADC group B channel 1 analog input, with full-scale range of 0 V to 3.3 V (or VREFHI/VREFLO ratiometric). |
| 14 | ADCINB2/COMP1B/AIO10 | input | ADC group B channel 2 analog input, also comparator 1B input and AIO10. |
| 15 | ADCINB3 | input | ADC group B channel 3 analog input, with full-scale range of 0 V to 3.3 V (or VREFHI/VREFLO ratiometric). |
| 16 | ADCINB4/COMP2B/AIO12 | input | ADC group B channel 4 analog input, also comparator 2B input (48-pin device only) and AIO12. |
| 17 | ADCINB6/AIO14 | input | ADC group B channel 6 analog input, also usable as digital AIO14. |
| 18 | ADCINB7 | input | ADC group B channel 7 analog input, with full-scale range of 0 V to 3.3 V (or VREFHI/VREFLO ratiometric). |
| 19 | GPIO34/COMP2OUT | bidirectional | General-purpose I/O 34 with comparator 2 direct output (48-pin only) and boot-mode select function; may glitch at power-up when the on-chip VREG is used. |
| 20 | GPIO35/TDI | bidirectional | General-purpose I/O 35 with JTAG test data input (TDI) on the rising edge of TCK and an internal pull-up; may glitch at power-up when the on-chip VREG is used. |
| 21 | GPIO36/TMS | bidirectional | General-purpose I/O 36 with JTAG test mode select (TMS) input to the TAP controller on TCK rising edge and an internal pull-up; Group 2 pin (8 mA). |
| 22 | GPIO37/TDO | bidirectional | General-purpose I/O 37 with JTAG test data output (TDO, 8 mA drive); also used for boot-mode selection, which is unavailable when a JTAG debug probe is connected. |
| 23 | GPIO38/XCLKIN/TCK | bidirectional | General-purpose I/O 38 with JTAG test clock (TCK, internal pull-up) and external oscillator input XCLKIN (default clock source); using it as external clock may conflict with JTAG debug. |
| 24 | GPIO18/SPICLKA/SCITXDA/XCLKOUT | bidirectional | General-purpose I/O 18 (Group 2, 8 mA) with SPI-A clock, SCI-A transmit and XCLKOUT output; XCLKOUT resets to SYSCLKOUT/4. |
| 25 | GPIO19/XCLKIN/SPISTEA/SCIRXDA/ECAP1 | bidirectional | General-purpose I/O 19 (Group 2, 8 mA) with external oscillator input XCLKIN, SPI-A slave transmit enable, SCI-A receive and eCAP1; may glitch at power-up when the on-chip VREG is used. |
| 26 | GPIO17/SPISOMIA/TZ3 | bidirectional | General-purpose I/O 17 (Group 2, 8 mA) with SPI-A slave output / master input and trip-zone 3; may glitch at power-up when the on-chip VREG is used. |
| 27 | GPIO16/SPISIMOA/TZ2 | bidirectional | General-purpose I/O 16 (Group 2, 8 mA) with SPI-A slave input / master output and trip-zone 2. |
| 28 | GPIO1/EPWM1B/COMP1OUT | bidirectional | General-purpose I/O 1 with ePWM1 output B and comparator 1 direct output. |
| 29 | GPIO0/EPWM1A | bidirectional | General-purpose I/O 0 with ePWM1 output A and HRPWM channel; GPIO0 can also feed XINT inputs. |
| 30 | TEST | unconnected | Reserved for TI; must be kept unconnected. |
| 31 | GPIO32/SDAA/EPWMSYNCI/ADCSOCAO | bidirectional | General-purpose I/O 32 with I2C-A data (open-drain), external ePWM sync input and ADC start-of-conversion A output. |
| 32 | VDD | power_in | CPU and logic digital supply; when the internal VREG is enabled a 1.2 µF (minimum) capacitor to ground is required on each VDD pin, and with VREG disabled it is supplied 1.71 V to 1.995 V (1.8 V nominal). |
| 33 | VSS | power_in | Digital ground pin. |
| 34 | VREGENZ | input | Internal regulator enable with internal pull-down; tie to VSS to enable the internal 1.8 V VREG, or tie to VDDIO to disable it and supply VDD externally. |
| 35 | VDDIO | power_in | Digital I/O and Flash supply, 2.97 V to 3.63 V (3.3 V nominal) with decoupling capacitor on this pin; single supply when VREG is enabled. |
| 36 | GPIO33/SCLA/EPWMSYNCO/ADCSOCBO | bidirectional | General-purpose I/O 33 with I2C-A clock (open-drain), external ePWM sync output and ADC start-of-conversion B output. |
| 37 | GPIO2/EPWM2A | bidirectional | General-purpose I/O 2 with ePWM2 output A and HRPWM channel. |
| 38 | GPIO3/EPWM2B/COMP2OUT | bidirectional | General-purpose I/O 3 with ePWM2 output B and comparator 2 direct output (48-pin only). |
| 39 | GPIO4/EPWM3A | bidirectional | General-purpose I/O 4 with ePWM3 output A and HRPWM channel. |
| 40 | GPIO5/EPWM3B/ECAP1 | bidirectional | General-purpose I/O 5 with ePWM3 output B and enhanced capture input/output 1 (eCAP1). |
| 41 | GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO | bidirectional | General-purpose I/O 6 with ePWM4 output A and HRPWM channel, plus external ePWM sync input and sync output. |
| 42 | GPIO7/EPWM4B/SCIRXDA | bidirectional | General-purpose I/O 7 with ePWM4 output B and SCI-A receive data input. |
| 43 | VDD | power_in | CPU and logic digital supply; when the internal VREG is enabled a 1.2 µF (minimum) capacitor to ground is required on each VDD pin. |
| 44 | VSS | power_in | Digital ground pin. |
| 45 | X1 | input | 1.8 V on-chip crystal oscillator input that must not be driven with 3.3 V signals; connect to GND if the oscillator is unused and use with X2 and a crystal or resonator when used. |
| 46 | X2 | output | On-chip crystal oscillator output; connect to X1 with a crystal or resonator, and leave unconnected if not used. |
| 47 | GPIO12/TZ1/SCITXDA | bidirectional | General-purpose I/O 12 with trip-zone 1 input and SCI-A transmit data output. |
| 48 | GPIO28/SCIRXDA/SDAA/TZ2 | bidirectional | General-purpose I/O 28 with SCI receive data input, I2C-A data (open-drain) and trip-zone 2 input. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 48 |
## CAD (KiCad official)
- Symbol: `TMS320F28027PTR`
- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`
- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files: `tms320f28027ptr-etched.step` / `tms320f28027ptr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tms320f28027ptr.step` / `tms320f28027ptr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tms320f28020) (147 pp, sha256 `b90c388f4142c4b5`, retrieved 2026-10-11, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tms320f28027ptr-datasheet.pdf)