component
TMS320F28023PTQ
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TMS320F28023PTQ
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)
TMS320F28023PTQ from Texas Instruments, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GPIO29/SCITXDA/SCLA/TZ3 | bidirectional | General-purpose I/O 29 with alternate functions SCI-A transmit, I2C-A clock (open-drain) and trip-zone input 3; inputs are not 5 V tolerant and the internal pull-up is enabled after reset. |
| 2 | TRST | input | JTAG test reset with internal pull-down that must be held low during normal operation and needs an external pull-up (about 2.2 kΩ typical, depending on debugger pod drive strength). |
| 3 | XRS | bidirectional | Open-drain device reset input and watchdog reset output with internal pull-up, driven low during power-up/brown-out and for 512 OSCCLK cycles on a watchdog reset; a 2.2 kΩ to 10 kΩ resistor to VDDIO is required. |
| 4 | ADCINA6/AIO6 | bidirectional | ADC group A channel 6 analog input, or digital AIO6 I/O when AIO function is selected; AIO pins have no internal pull-up. |
| 5 | ADCINA4/COMP2A/AIO4 | bidirectional | ADC group A channel 4 analog input, comparator 2A input (48-pin package only), or digital AIO4 I/O. |
| 6 | ADCINA7 | input | ADC group A channel 7 analog input. |
| 7 | ADCINA3 | input | ADC group A channel 3 analog input. |
| 8 | ADCINA1 | input | ADC group A channel 1 analog input. |
| 9 | ADCINA2/COMP1A/AIO2 | bidirectional | ADC group A channel 2 analog input, comparator 1A input, or digital AIO2 I/O. |
| 10 | ADCINA0/VREFHI | input | ADC group A channel 0 analog input; VREFHI is the external ADC reference high used only in external reference mode and must not exceed VDDA. |
| 11 | VDDA | power_in | Analog supply, 2.97 V to 3.63 V (3.3 V nominal); place a 2.2 µF capacitor (typical) near this pin. |
| 12 | VSSA/VREFLO | power_in | Analog ground, also the ADC external reference low (VREFLO), which is always grounded. |
| 13 | ADCINB1 | input | ADC group B channel 1 analog input. |
| 14 | ADCINB2/COMP1B/AIO10 | bidirectional | ADC group B channel 2 analog input, comparator 1B input, or digital AIO10 I/O. |
| 15 | ADCINB3 | input | ADC group B channel 3 analog input. |
| 16 | ADCINB4/COMP2B/AIO12 | bidirectional | ADC group B channel 4 analog input, comparator 2B input (48-pin package only), or digital AIO12 I/O. |
| 17 | ADCINB6/AIO14 | bidirectional | ADC group B channel 6 analog input or digital AIO14 I/O; AIO pins have no internal pull-up. |
| 18 | ADCINB7 | input | ADC group B channel 7 analog input. |
| 19 | GPIO34/COMP2OUT | bidirectional | General-purpose I/O 34 or comparator 2 direct output (COMP2OUT, 48-pin only); may glitch during power-up when the internal VREG is used. |
| 20 | GPIO35/TDI | bidirectional | General-purpose I/O 35 or JTAG test data input (TDI) with internal pull-up, sampled on the rising edge of TCK; may glitch during power-up when the internal VREG is used. |
| 21 | GPIO36/TMS | bidirectional | General-purpose I/O 36 or JTAG test mode select (TMS) with internal pull-up, sampled on the rising edge of TCK; may glitch during power-up when the internal VREG is used. |
| 22 | GPIO37/TDO | tri_state | General-purpose I/O 37 or JTAG test data output (TDO), 8 mA drive, shifted out on the falling edge of TCK; may glitch during power-up when the internal VREG is used. |
| 23 | GPIO38/TCK/XCLKIN | bidirectional | General-purpose I/O 38, JTAG test clock (TCK) with internal pull-up, or external oscillator input XCLKIN (default clock-source selection). |
| 24 | GPIO18/SPICLKA/SCITXDA/XCLKOUT | bidirectional | General-purpose I/O 18, SPI-A clock, SCI-A transmit, or XCLKOUT (SYSCLKOUT-derived, reset to SYSCLKOUT/4); a group 2 pin limited to 4 mA source/sink (8 mA group 2 option per the datasheet table). |
| 25 | GPIO19/XCLKIN/SPISTEA/SCIRXDA/ECAP1 | bidirectional | General-purpose I/O 19, external oscillator input XCLKIN, SPI-A slave transmit enable, SCI-A receive or eCAP1 I/O; may glitch during power-up when the internal VREG is used. |
| 26 | GPIO17/SPISOMIA/TZ3 | bidirectional | General-purpose I/O 17, SPI-A slave output (master input), or trip-zone input 3. |
| 27 | GPIO16/SPISIMOA/TZ2 | bidirectional | General-purpose I/O 16, SPI-A slave input (master output), or trip-zone input 2. |
| 28 | GPIO1/EPWM1B/COMP1OUT | bidirectional | General-purpose I/O 1, ePWM1B output, or comparator 1 direct output (COMP1OUT). |
| 29 | GPIO0/EPWM1A | bidirectional | General-purpose I/O 0 or ePWM1A output (with HRPWM channel); PWM pins have no pull-up enabled at reset. |
| 30 | TEST | bidirectional | Reserved for TI test; must be left unconnected. |
| 31 | GPIO32/SDAA/EPWMSYNCI/ADCSOCAO | bidirectional | General-purpose I/O 32, I2C-A data (open-drain), ePWM external sync input, or ADC start-of-conversion A output. |
| 32 | VDD | power_in | CPU and logic digital supply; when the internal VREG is used a 1.2 µF (minimum) capacitor is required on each VDD pin, and when VREG is disabled it must be supplied at 1.71 V to 1.995 V (1.8 V nominal). |
| 33 | VSS | power_in | Digital ground. |
| 34 | VREGENZ | input | Internal regulator enable with internal pull-down: tie to VSS to enable the internal 1.8 V VREG, or to VDDIO to disable it and use an external 1.8 V supply. |
| 35 | VDDIO | power_in | Digital I/O buffer and flash supply, 2.97 V to 3.63 V (3.3 V nominal); a decoupling capacitor is required on this pin. |
| 36 | GPIO33/SCLA/EPWMSYNCO/ADCSOCBO | bidirectional | General-purpose I/O 33, I2C-A clock (open-drain), ePWM external sync output, or ADC start-of-conversion B output. |
| 37 | GPIO2/EPWM2A | bidirectional | General-purpose I/O 2 or ePWM2A output (with HRPWM channel). |
| 38 | GPIO3/EPWM2B/COMP2OUT | bidirectional | General-purpose I/O 3, ePWM2B output, or comparator 2 direct output (COMP2OUT, 48-pin only). |
| 39 | GPIO4/EPWM3A | bidirectional | General-purpose I/O 4 or ePWM3A output (with HRPWM channel). |
| 40 | GPIO5/EPWM3B/ECAP1 | bidirectional | General-purpose I/O 5, ePWM3B output, or eCAP1 input/output. |
| 41 | GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO | bidirectional | General-purpose I/O 6, ePWM4A output (with HRPWM channel), or external ePWM sync input/output. |
| 42 | GPIO7/EPWM4B/SCIRXDA | bidirectional | General-purpose I/O 7, ePWM4B output, or SCI-A receive data. |
| 43 | VDD | power_in | CPU and logic digital supply; same requirements as pin 32 (1.2 µF per VDD pin with internal VREG, 1.71 V to 1.995 V if VREG is disabled). |
| 44 | VSS | power_in | Digital ground. |
| 45 | X1 | input | 1.8 V on-chip crystal oscillator input that must never receive 3.3 V signals; connect to GND if unused, and it is used together with X2 and a crystal or resonator. |
| 46 | X2 | output | On-chip crystal oscillator output that must be connected to X2's crystal/resonator with X1; leave unconnected if unused. |
| 47 | GPIO12/TZ1/SCITXDA | bidirectional | General-purpose I/O 12, trip-zone input 1, or SCI-A transmit data. |
| 48 | GPIO28/SCIRXDA/SDAA/TZ2 | bidirectional | General-purpose I/O 28, SCI receive data, I2C-A data (open-drain), or trip-zone input 2; a group 2 pin with reduced drive strength. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 48 |
CAD (KiCad official)
- Symbol:
TMS320F28023PTQ - Footprint:
Package_QFP:LQFP-48_7x7mm_P0.5mm - 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
tms320f28023ptq-etched.step/tms320f28023ptq-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tms320f28023ptq.step/tms320f28023ptq.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (147 pp, sha256
b90c388f4142c4b5, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TMS320F28023PTQ
**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)
TMS320F28023PTQ from Texas Instruments, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GPIO29/SCITXDA/SCLA/TZ3 | bidirectional | General-purpose I/O 29 with alternate functions SCI-A transmit, I2C-A clock (open-drain) and trip-zone input 3; inputs are not 5 V tolerant and the internal pull-up is enabled after reset. |
| 2 | TRST | input | JTAG test reset with internal pull-down that must be held low during normal operation and needs an external pull-up (about 2.2 kΩ typical, depending on debugger pod drive strength). |
| 3 | XRS | bidirectional | Open-drain device reset input and watchdog reset output with internal pull-up, driven low during power-up/brown-out and for 512 OSCCLK cycles on a watchdog reset; a 2.2 kΩ to 10 kΩ resistor to VDDIO is required. |
| 4 | ADCINA6/AIO6 | bidirectional | ADC group A channel 6 analog input, or digital AIO6 I/O when AIO function is selected; AIO pins have no internal pull-up. |
| 5 | ADCINA4/COMP2A/AIO4 | bidirectional | ADC group A channel 4 analog input, comparator 2A input (48-pin package only), or digital AIO4 I/O. |
| 6 | ADCINA7 | input | ADC group A channel 7 analog input. |
| 7 | ADCINA3 | input | ADC group A channel 3 analog input. |
| 8 | ADCINA1 | input | ADC group A channel 1 analog input. |
| 9 | ADCINA2/COMP1A/AIO2 | bidirectional | ADC group A channel 2 analog input, comparator 1A input, or digital AIO2 I/O. |
| 10 | ADCINA0/VREFHI | input | ADC group A channel 0 analog input; VREFHI is the external ADC reference high used only in external reference mode and must not exceed VDDA. |
| 11 | VDDA | power_in | Analog supply, 2.97 V to 3.63 V (3.3 V nominal); place a 2.2 µF capacitor (typical) near this pin. |
| 12 | VSSA/VREFLO | power_in | Analog ground, also the ADC external reference low (VREFLO), which is always grounded. |
| 13 | ADCINB1 | input | ADC group B channel 1 analog input. |
| 14 | ADCINB2/COMP1B/AIO10 | bidirectional | ADC group B channel 2 analog input, comparator 1B input, or digital AIO10 I/O. |
| 15 | ADCINB3 | input | ADC group B channel 3 analog input. |
| 16 | ADCINB4/COMP2B/AIO12 | bidirectional | ADC group B channel 4 analog input, comparator 2B input (48-pin package only), or digital AIO12 I/O. |
| 17 | ADCINB6/AIO14 | bidirectional | ADC group B channel 6 analog input or digital AIO14 I/O; AIO pins have no internal pull-up. |
| 18 | ADCINB7 | input | ADC group B channel 7 analog input. |
| 19 | GPIO34/COMP2OUT | bidirectional | General-purpose I/O 34 or comparator 2 direct output (COMP2OUT, 48-pin only); may glitch during power-up when the internal VREG is used. |
| 20 | GPIO35/TDI | bidirectional | General-purpose I/O 35 or JTAG test data input (TDI) with internal pull-up, sampled on the rising edge of TCK; may glitch during power-up when the internal VREG is used. |
| 21 | GPIO36/TMS | bidirectional | General-purpose I/O 36 or JTAG test mode select (TMS) with internal pull-up, sampled on the rising edge of TCK; may glitch during power-up when the internal VREG is used. |
| 22 | GPIO37/TDO | tri_state | General-purpose I/O 37 or JTAG test data output (TDO), 8 mA drive, shifted out on the falling edge of TCK; may glitch during power-up when the internal VREG is used. |
| 23 | GPIO38/TCK/XCLKIN | bidirectional | General-purpose I/O 38, JTAG test clock (TCK) with internal pull-up, or external oscillator input XCLKIN (default clock-source selection). |
| 24 | GPIO18/SPICLKA/SCITXDA/XCLKOUT | bidirectional | General-purpose I/O 18, SPI-A clock, SCI-A transmit, or XCLKOUT (SYSCLKOUT-derived, reset to SYSCLKOUT/4); a group 2 pin limited to 4 mA source/sink (8 mA group 2 option per the datasheet table). |
| 25 | GPIO19/XCLKIN/SPISTEA/SCIRXDA/ECAP1 | bidirectional | General-purpose I/O 19, external oscillator input XCLKIN, SPI-A slave transmit enable, SCI-A receive or eCAP1 I/O; may glitch during power-up when the internal VREG is used. |
| 26 | GPIO17/SPISOMIA/TZ3 | bidirectional | General-purpose I/O 17, SPI-A slave output (master input), or trip-zone input 3. |
| 27 | GPIO16/SPISIMOA/TZ2 | bidirectional | General-purpose I/O 16, SPI-A slave input (master output), or trip-zone input 2. |
| 28 | GPIO1/EPWM1B/COMP1OUT | bidirectional | General-purpose I/O 1, ePWM1B output, or comparator 1 direct output (COMP1OUT). |
| 29 | GPIO0/EPWM1A | bidirectional | General-purpose I/O 0 or ePWM1A output (with HRPWM channel); PWM pins have no pull-up enabled at reset. |
| 30 | TEST | bidirectional | Reserved for TI test; must be left unconnected. |
| 31 | GPIO32/SDAA/EPWMSYNCI/ADCSOCAO | bidirectional | General-purpose I/O 32, I2C-A data (open-drain), ePWM external sync input, or ADC start-of-conversion A output. |
| 32 | VDD | power_in | CPU and logic digital supply; when the internal VREG is used a 1.2 µF (minimum) capacitor is required on each VDD pin, and when VREG is disabled it must be supplied at 1.71 V to 1.995 V (1.8 V nominal). |
| 33 | VSS | power_in | Digital ground. |
| 34 | VREGENZ | input | Internal regulator enable with internal pull-down: tie to VSS to enable the internal 1.8 V VREG, or to VDDIO to disable it and use an external 1.8 V supply. |
| 35 | VDDIO | power_in | Digital I/O buffer and flash supply, 2.97 V to 3.63 V (3.3 V nominal); a decoupling capacitor is required on this pin. |
| 36 | GPIO33/SCLA/EPWMSYNCO/ADCSOCBO | bidirectional | General-purpose I/O 33, I2C-A clock (open-drain), ePWM external sync output, or ADC start-of-conversion B output. |
| 37 | GPIO2/EPWM2A | bidirectional | General-purpose I/O 2 or ePWM2A output (with HRPWM channel). |
| 38 | GPIO3/EPWM2B/COMP2OUT | bidirectional | General-purpose I/O 3, ePWM2B output, or comparator 2 direct output (COMP2OUT, 48-pin only). |
| 39 | GPIO4/EPWM3A | bidirectional | General-purpose I/O 4 or ePWM3A output (with HRPWM channel). |
| 40 | GPIO5/EPWM3B/ECAP1 | bidirectional | General-purpose I/O 5, ePWM3B output, or eCAP1 input/output. |
| 41 | GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO | bidirectional | General-purpose I/O 6, ePWM4A output (with HRPWM channel), or external ePWM sync input/output. |
| 42 | GPIO7/EPWM4B/SCIRXDA | bidirectional | General-purpose I/O 7, ePWM4B output, or SCI-A receive data. |
| 43 | VDD | power_in | CPU and logic digital supply; same requirements as pin 32 (1.2 µF per VDD pin with internal VREG, 1.71 V to 1.995 V if VREG is disabled). |
| 44 | VSS | power_in | Digital ground. |
| 45 | X1 | input | 1.8 V on-chip crystal oscillator input that must never receive 3.3 V signals; connect to GND if unused, and it is used together with X2 and a crystal or resonator. |
| 46 | X2 | output | On-chip crystal oscillator output that must be connected to X2's crystal/resonator with X1; leave unconnected if unused. |
| 47 | GPIO12/TZ1/SCITXDA | bidirectional | General-purpose I/O 12, trip-zone input 1, or SCI-A transmit data. |
| 48 | GPIO28/SCIRXDA/SDAA/TZ2 | bidirectional | General-purpose I/O 28, SCI receive data, I2C-A data (open-drain), or trip-zone input 2; a group 2 pin with reduced drive strength. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 48 |
## CAD (KiCad official)
- Symbol: `TMS320F28023PTQ`
- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`
- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files: `tms320f28023ptq-etched.step` / `tms320f28023ptq-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tms320f28023ptq.step` / `tms320f28023ptq.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tms320f28020) (147 pp, sha256 `b90c388f4142c4b5`, retrieved 2026-10-08, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tms320f28023ptq-datasheet.pdf)