component
TMS320F280230PTT
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+85@@ -0,0 +1,85 @@+# TMS320F280230PTT++**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)++TMS320F280230PTT from Texas Instruments, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GPIO29/SCITXDA/SCLA/TZ3 | bidirectional | General-purpose I/O 29 (default GPIO at reset) with alternate SCI-A transmit, I2C clock SCLA (open-drain) and trip-zone 3 input functions; inputs are not 5-V tolerant. |+| 2 | TRST | input | JTAG test reset with internal pulldown that must be kept low during normal operation, and an external pulldown resistor is required (2.2 kΩ generally offers adequate protection). |+| 3 | XRS | bidirectional | Device reset input and watchdog reset output, open-drain with internal pullup, driven low during power-on/brown-out and for 512 OSCCLK cycles on a watchdog reset; an R-C circuit is recommended for noise immunity. |+| 4 | ADCINA6/AIO6 | passive | ADC Group A channel 6 analog input, or digital analog I/O AIO6 when selected; AIO pins have no internal pullup. |+| 5 | ADCINA4/COMP2A/AIO4 | passive | ADC Group A channel 4 analog input, Comparator 2A input (48-pin device), or digital analog I/O AIO4; AIO pins have no internal pullup. |+| 6 | VSSA | power_in | Analog ground pin. |+| 7 | VSSA | power_in | Analog ground pin. |+| 8 | ADCINA1 | passive | ADC Group A channel 1 analog input. |+| 9 | ADCINA2/COMP1A/AIO2 | passive | ADC Group A channel 2 analog input, Comparator 1A input, or digital analog I/O AIO2; AIO pins have no internal pullup. |+| 10 | VREFHI | input | ADC external high reference, used only in external reference mode, and must not exceed VDDA. |+| 11 | VDDA | power_in | Analog power pin, recommended 2.97 V to 3.63 V (3.3 V nominal), tied with a 2.2-µF (typical) capacitor close to the pin and kept within approximately 0.3 V of VDDIO. |+| 12 | VSSA/VREFLO | power_in | Analog ground pin that doubles as the ADC low reference VREFLO, which is always tied to ground. |+| 13 | ADCINB1 | passive | ADC Group B channel 1 analog input. |+| 14 | ADCINB2/COMP1B/AIO10 | passive | ADC Group B channel 2 analog input, Comparator 1B input, or digital analog I/O AIO10; AIO pins have no internal pullup. |+| 15 | VSSA | power_in | Analog ground pin. |+| 16 | ADCINB4/COMP2B/AIO12 | passive | ADC Group B channel 4 analog input, Comparator 2B input (48-pin device), or digital analog I/O AIO12; AIO pins have no internal pullup. |+| 17 | ADCINB6/AIO14 | passive | ADC Group B channel 6 analog input, or digital analog I/O AIO14; AIO pins have no internal pullup. |+| 18 | VSSA | power_in | Analog ground pin. |+| 19 | GPIO34/COMP2OUT | bidirectional | General-purpose I/O 34 with direct Comparator 2 output COMP2OUT; pin may glitch during power-up when the on-chip VREG is used. |+| 20 | GPIO35 (TDI) | bidirectional | General-purpose I/O 35 with JTAG test data input TDI (internal pullup); pin may glitch during power-up when the on-chip VREG is used. |+| 21 | GPIO36 (TMS) | bidirectional | General-purpose I/O 36 with JTAG test-mode select TMS (internal pullup), clocked into the TAP controller on the rising edge of TCK; pin may glitch during power-up when the on-chip VREG is used. |+| 22 | GPIO37/TDO | bidirectional | General-purpose I/O 37 with JTAG test data output TDO, shifted out on the falling edge of TCK with 8-mA drive; pin may glitch during power-up when the on-chip VREG is used. |+| 23 | GPIO38/XCLKIN (TCK) | bidirectional | General-purpose I/O 38 with JTAG test clock TCK (internal pullup) and external oscillator input XCLKIN; do not enable the XCLKIN clock path while TCK is active during JTAG debug. |+| 24 | GPIO18/SPICLKA/SCITXDA/XCLKOUT | bidirectional | General-purpose I/O 18 with SPI-A clock, SCI-A transmit and XCLKOUT functions; XCLKOUT is SYSCLKOUT, /2 or /4 (SYSCLKOUT/4 at reset) and requires the GPIO18 mux set to XCLKOUT. |+| 25 | GPIO19/XCLKIN/SPISTEA/SCIRXDA/ECAP1 | bidirectional | General-purpose I/O 19 with SPI-A STE, SCI-A receive, ECAP1 and external oscillator input XCLKIN functions; the XCLKIN path is not gated by the pin mux, so it must not be enabled when the pin is used for other peripherals. |+| 26 | GPIO17/SPISOMIA/TZ3 | bidirectional | General-purpose I/O 17 with SPI-A slave-out/master-in and trip-zone 3 input functions. |+| 27 | GPIO16/SPISIMOA/TZ2 | bidirectional | General-purpose I/O 16 with SPI-A slave-in/master-out and trip-zone 2 input functions. |+| 28 | GPIO1/EPWM1B/COMP1OUT | bidirectional | General-purpose I/O 1 with ePWM1B output and direct Comparator 1 output COMP1OUT functions; PWM pin pullups are not enabled at reset. |+| 29 | GPIO0/EPWM1A | bidirectional | General-purpose I/O 0 with ePWM1A output function; PWM pin pullups are not enabled at reset. |+| 30 | TEST | unconnected | Test pin reserved for TI that must be left unconnected. |+| 31 | GPIO32/SDAA/EPWMSYNCI/ADCSOCAO | bidirectional | General-purpose I/O 32 with I2C data SDAA (open-drain), ePWM external sync input and ADC start-of-conversion A output functions. |+| 32 | VDD | power_in | CPU and logic digital power pin; no external supply is needed with the internal VREG, which requires a 1.2-µF minimum ceramic capacitor (10% tolerance) to ground, and 1.71 V to 1.995 V must be supplied externally if VREG is disabled. |+| 33 | VSS | power_in | Digital ground pin. |+| 34 | VREGENZ | input | Internal voltage regulator enable input; pull low to enable the internal VREG and pull high to disable it. |+| 35 | VDDIO | power_in | Digital I/O and flash power pin, 2.97 V to 3.63 V (3.3 V nominal), the single supply source when VREG is enabled, tied with a 2.2-µF (typical) capacitor close to the pin. |+| 36 | GPIO33/SCLA/EPWMSYNCO/ADCSOCBO | bidirectional | General-purpose I/O 33 with I2C clock SCLA (open-drain), ePWM external sync output and ADC start-of-conversion B output functions. |+| 37 | GPIO2/EPWM2A | bidirectional | General-purpose I/O 2 with ePWM2A output function; PWM pin pullups are not enabled at reset. |+| 38 | GPIO3/EPWM2B/COMP2OUT | bidirectional | General-purpose I/O 3 with ePWM2B output and direct Comparator 2 output COMP2OUT (48-pin device) functions. |+| 39 | GPIO4/EPWM3A | bidirectional | General-purpose I/O 4 with ePWM3A output function. |+| 40 | GPIO5/EPWM3B/ECAP1 | bidirectional | General-purpose I/O 5 with ePWM3B output and enhanced capture 1 input/output (ECAP1) functions. |+| 41 | GPIO6/EPWMSYNCI/EPWMSYNCO | bidirectional | General-purpose I/O 6 with ePWM external sync input EPWMSYNCI and sync output EPWMSYNCO functions. |+| 42 | GPIO7/SCIRXDA | bidirectional | General-purpose I/O 7 with SCI-A receive data input function. |+| 43 | VDD | power_in | CPU and logic digital power pin, with the same 1.2-µF minimum ceramic capacitor requirement when the internal VREG is used. |+| 44 | VSS | power_in | Digital ground pin. |+| 45 | X1 | input | On-chip crystal oscillator input; a quartz crystal or ceramic resonator is connected across X1 and X2, and the pin must be tied to GND if not used. |+| 46 | X2 | output | On-chip crystal oscillator output; a quartz crystal or ceramic resonator is connected across X1 and X2, and the pin must be left unconnected if not used. |+| 47 | GPIO12/TZ1/SCITXDA | bidirectional | General-purpose I/O 12 with trip-zone 1 input and SCI-A transmit output functions. |+| 48 | GPIO28/SCIRXDA/SDAA/TZ2 | bidirectional | General-purpose I/O 28 with SCI receive data, I2C data SDAA (open-drain) and trip-zone 2 input functions. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | LQFP-48(7x7) |+| Category | Embedded Processors & Controllers |+| Pins | 48 |++## CAD (KiCad official)++- Symbol: `TMS320F280230PTT`+- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`+- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)+- 3D model files: `tms320f280230ptt-etched.step` / `tms320f280230ptt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tms320f280230ptt.step` / `tms320f280230ptt.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tms320f280270) (131 pp, sha256 `c31e28b9bb70e614`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tms320f280230ptt-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "tms320f280230ptt",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tms320f280230ptt.kicad_sym",+ "tms320f280230ptt.kicad_mod",+ "tms320f280230ptt.glb",+ "tms320f280230ptt.step",+ "tms320f280230ptt.lbr",+ "docs/hero.png",+ "docs/tms320f280230ptt-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tms320f280230ptt-hero.glb",+ "tms320f280230ptt-hero.overlay.json"+ ],+ "component": {+ "mpn": "TMS320F280230PTT",+ "manufacturer": "Texas Instruments",+ "package": "LQFP-48(7x7)",+ "pin_count": 48,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tms320f280270",+ "parts": {+ "symbol": "tms320f280230ptt.kicad_sym",+ "footprint": "tms320f280230ptt.kicad_mod",+ "model_3d": "tms320f280230ptt-hero.glb",+ "model_3d_plain": "tms320f280230ptt.glb",+ "model_3d_step": "tms320f280230ptt-etched.step",+ "model_3d_step_plain": "tms320f280230ptt.step",+ "lbr": "tms320f280230ptt.lbr"+ },+ "distributor_links": {+ "lcsc": "C504361",+ "digikey": "296-48058-ND",+ "mouser": "595-TMS320F280230PTT"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T19:54:46Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-48058-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-TMS320F280230PTT",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "GPIO29/SCITXDA/SCLA/TZ3",+ "type": "bidirectional",+ "description": "General-purpose I/O 29 (default GPIO at reset) with alternate SCI-A transmit, I2C clock SCLA (open-drain) and trip-zone 3 input functions; inputs are not 5-V tolerant."+ },+ {+ "number": "2",+ "name": "TRST",+ "type": "input",+ "description": "JTAG test reset with internal pulldown that must be kept low during normal operation, and an external pulldown resistor is required (2.2 kΩ generally offers adequate protection)."+ },+ {+ "number": "3",+ "name": "XRS",+ "type": "bidirectional",+ "description": "Device reset input and watchdog reset output, open-drain with internal pullup, driven low during power-on/brown-out and for 512 OSCCLK cycles on a watchdog reset; an R-C circuit is recommended for noise immunity."+ },+ {+ "number": "4",+ "name": "ADCINA6/AIO6",+ "type": "passive",+ "description": "ADC Group A channel 6 analog input, or digital analog I/O AIO6 when selected; AIO pins have no internal pullup."+ },+ {+ "number": "5",+ "name": "ADCINA4/COMP2A/AIO4",+ "type": "passive",+ "description": "ADC Group A channel 4 analog input, Comparator 2A input (48-pin device), or digital analog I/O AIO4; AIO pins have no internal pullup."+ },+ {+ "number": "6",+ "name": "VSSA",+ "type": "power_in",+ "description": "Analog ground pin."+ },+ {+ "number": "7",+ "name": "VSSA",+ "type": "power_in",+ "description": "Analog ground pin."+ },+ {+ "number": "8",+ "name": "ADCINA1",+ "type": "passive",+ "description": "ADC Group A channel 1 analog input."+ },+ {+ "number": "9",+ "name": "ADCINA2/COMP1A/AIO2",+ "type": "passive",+ "description": "ADC Group A channel 2 analog input, Comparator 1A input, or digital analog I/O AIO2; AIO pins have no internal pullup."+ },+ {+ "number": "10",+ "name": "VREFHI",+ "type": "input",+ "description": "ADC external high reference, used only in external reference mode, and must not exceed VDDA."+ },+ {+ "number": "11",+ "name": "VDDA",+ "type": "power_in",+ "description": "Analog power pin, recommended 2.97 V to 3.63 V (3.3 V nominal), tied with a 2.2-µF (typical) capacitor close to the pin and kept within approximately 0.3 V of VDDIO."+ },+ {+ "number": "12",+ "name": "VSSA/VREFLO",+ "type": "power_in",+ "description": "Analog ground pin that doubles as the ADC low reference VREFLO, which is always tied to ground."+ },+ {+ "number": "13",+ "name": "ADCINB1",+ "type": "passive",+ "description": "ADC Group B channel 1 analog input."+ },+ {+ "number": "14",+ "name": "ADCINB2/COMP1B/AIO10",+ "type": "passive",+ "description": "ADC Group B channel 2 analog input, Comparator 1B input, or digital analog I/O AIO10; AIO pins have no internal pullup."+ },+ {+ "number": "15",+ "name": "VSSA",+ "type": "power_in",+ "description": "Analog ground pin."+ },+ {+ "number": "16",+ "name": "ADCINB4/COMP2B/AIO12",+ "type": "passive",+ "description": "ADC Group B channel 4 analog input, Comparator 2B input (48-pin device), or digital analog I/O AIO12; AIO pins have no internal pullup."+ },+ {+ "number": "17",+ "name": "ADCINB6/AIO14",+ "type": "passive",+ "description": "ADC Group B channel 6 analog input, or digital analog I/O AIO14; AIO pins have no internal pullup."+ },+ {+ "number": "18",+ "name": "VSSA",+ "type": "power_in",+ "description": "Analog ground pin."+ },+ {+ "number": "19",+ "name": "GPIO34/COMP2OUT",+ "type": "bidirectional",+ "description": "General-purpose I/O 34 with direct Comparator 2 output COMP2OUT; pin may glitch during power-up when the on-chip VREG is used."+ },+ {+ "number": "20",+ "name": "GPIO35 (TDI)",+ "type": "bidirectional",+ "description": "General-purpose I/O 35 with JTAG test data input TDI (internal pullup); pin may glitch during power-up when the on-chip VREG is used."+ },+ {+ "number": "21",+ "name": "GPIO36 (TMS)",+ "type": "bidirectional",+ "description": "General-purpose I/O 36 with JTAG test-mode select TMS (internal pullup), clocked into the TAP controller on the rising edge of TCK; pin may glitch during power-up when the on-chip VREG is used."+ },+ {+ "number": "22",+ "name": "GPIO37/TDO",+ "type": "bidirectional",+ "description": "General-purpose I/O 37 with JTAG test data output TDO, shifted out on the falling edge of TCK with 8-mA drive; pin may glitch during power-up when the on-chip VREG is used."+ },+ {+ "number": "23",+ "name": "GPIO38/XCLKIN (TCK)",+ "type": "bidirectional",+ "description": "General-purpose I/O 38 with JTAG test clock TCK (internal pullup) and external oscillator input XCLKIN; do not enable the XCLKIN clock path while TCK is active during JTAG debug."+ },+ {+ "number": "24",+ "name": "GPIO18/SPICLKA/SCITXDA/XCLKOUT",+ "type": "bidirectional",+ "description": "General-purpose I/O 18 with SPI-A clock, SCI-A transmit and XCLKOUT functions; XCLKOUT is SYSCLKOUT, /2 or /4 (SYSCLKOUT/4 at reset) and requires the GPIO18 mux set to XCLKOUT."+ },+ {+ "number": "25",+ "name": "GPIO19/XCLKIN/SPISTEA/SCIRXDA/ECAP1",+ "type": "bidirectional",+ "description": "General-purpose I/O 19 with SPI-A STE, SCI-A receive, ECAP1 and external oscillator input XCLKIN functions; the XCLKIN path is not gated by the pin mux, so it must not be enabled when the pin is used for other peripherals."+ },+ {+ "number": "26",+ "name": "GPIO17/SPISOMIA/TZ3",+ "type": "bidirectional",+ "description": "General-purpose I/O 17 with SPI-A slave-out/master-in and trip-zone 3 input functions."+ },+ {+ "number": "27",+ "name": "GPIO16/SPISIMOA/TZ2",+ "type": "bidirectional",+ "description": "General-purpose I/O 16 with SPI-A slave-in/master-out and trip-zone 2 input functions."+ },+ {+ "number": "28",+ "name": "GPIO1/EPWM1B/COMP1OUT",+ "type": "bidirectional",+ "description": "General-purpose I/O 1 with ePWM1B output and direct Comparator 1 output COMP1OUT functions; PWM pin pullups are not enabled at reset."+ },+ {+ "number": "29",+ "name": "GPIO0/EPWM1A",+ "type": "bidirectional",+ "description": "General-purpose I/O 0 with ePWM1A output function; PWM pin pullups are not enabled at reset."+ },+ {+ "number": "30",+ "name": "TEST",+ "type": "unconnected",+ "description": "Test pin reserved for TI that must be left unconnected."+ },+ {+ "number": "31",+ "name": "GPIO32/SDAA/EPWMSYNCI/ADCSOCAO",+ "type": "bidirectional",+ "description": "General-purpose I/O 32 with I2C data SDAA (open-drain), ePWM external sync input and ADC start-of-conversion A output functions."+ },+ {+ "number": "32",+ "name": "VDD",+ "type": "power_in",+ "description": "CPU and logic digital power pin; no external supply is needed with the internal VREG, which requires a 1.2-µF minimum ceramic capacitor (10% tolerance) to ground, and 1.71 V to 1.995 V must be supplied externally if VREG is disabled."+ },+ {+ "number": "33",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin."+ },+ {+ "number": "34",+ "name": "VREGENZ",+ "type": "input",+ "description": "Internal voltage regulator enable input; pull low to enable the internal VREG and pull high to disable it."+ },+ {+ "number": "35",+ "name": "VDDIO",+ "type": "power_in",+ "description": "Digital I/O and flash power pin, 2.97 V to 3.63 V (3.3 V nominal), the single supply source when VREG is enabled, tied with a 2.2-µF (typical) capacitor close to the pin."+ },+ {+ "number": "36",+ "name": "GPIO33/SCLA/EPWMSYNCO/ADCSOCBO",+ "type": "bidirectional",+ "description": "General-purpose I/O 33 with I2C clock SCLA (open-drain), ePWM external sync output and ADC start-of-conversion B output functions."+ },+ {+ "number": "37",+ "name": "GPIO2/EPWM2A",+ "type": "bidirectional",+ "description": "General-purpose I/O 2 with ePWM2A output function; PWM pin pullups are not enabled at reset."+ },+ {+ "number": "38",+ "name": "GPIO3/EPWM2B/COMP2OUT",+ "type": "bidirectional",+ "description": "General-purpose I/O 3 with ePWM2B output and direct Comparator 2 output COMP2OUT (48-pin device) functions."+ },+ {+ "number": "39",+ "name": "GPIO4/EPWM3A",+ "type": "bidirectional",+ "description": "General-purpose I/O 4 with ePWM3A output function."+ },+ {+ "number": "40",+ "name": "GPIO5/EPWM3B/ECAP1",+ "type": "bidirectional",+ "description": "General-purpose I/O 5 with ePWM3B output and enhanced capture 1 input/output (ECAP1) functions."+ },+ {+ "number": "41",+ "name": "GPIO6/EPWMSYNCI/EPWMSYNCO",+ "type": "bidirectional",+ "description": "General-purpose I/O 6 with ePWM external sync input EPWMSYNCI and sync output EPWMSYNCO functions."+ },+ {+ "number": "42",+ "name": "GPIO7/SCIRXDA",+ "type": "bidirectional",+ "description": "General-purpose I/O 7 with SCI-A receive data input function."+ },+ {+ "number": "43",+ "name": "VDD",+ "type": "power_in",+ "description": "CPU and logic digital power pin, with the same 1.2-µF minimum ceramic capacitor requirement when the internal VREG is used."+ },+ {+ "number": "44",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin."+ },+ {+ "number": "45",+ "name": "X1",+ "type": "input",+ "description": "On-chip crystal oscillator input; a quartz crystal or ceramic resonator is connected across X1 and X2, and the pin must be tied to GND if not used."+ },+ {+ "number": "46",+ "name": "X2",+ "type": "output",+ "description": "On-chip crystal oscillator output; a quartz crystal or ceramic resonator is connected across X1 and X2, and the pin must be left unconnected if not used."+ },+ {+ "number": "47",+ "name": "GPIO12/TZ1/SCITXDA",+ "type": "bidirectional",+ "description": "General-purpose I/O 12 with trip-zone 1 input and SCI-A transmit output functions."+ },+ {+ "number": "48",+ "name": "GPIO28/SCIRXDA/SDAA/TZ2",+ "type": "bidirectional",+ "description": "General-purpose I/O 28 with SCI receive data, I2C data SDAA (open-drain) and trip-zone 2 input functions."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The LQFP-48 (7x7) body size from the package hint is not stated anywhere in the supplied pages. The ; The pin-assignment figure (page 32) text is garbled, so pin numbers and names were taken from the PT; Pin 30 TEST is typed as unconnected because the datasheet says it must be left unconnected. The tabl"+ ],+ "pages_sent": 44,+ "cost_usd": 0.2648,+ "at": "2026-10-08T19:54:16"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tms320f280270",+ "pages": 131,+ "sha256": "c31e28b9bb70e614",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 48,+ "described": 48,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tms320f280230ptt.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "9dea352d93177c2904afd7d7b68ea8855ce1ab691f69f8b3e13655600514b6bf",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tms320f280230ptt-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "4eb970c23d71146daee4023706b5047657229164c9d3e98b135e5aea52292c3e",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}