component
TMS320F280230PTT
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTMS320F280230PTT
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)
TMS320F280230PTT from Texas Instruments, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GPIO29/SCITXDA/SCLA/TZ3 | bidirectional | General-purpose I/O 29 (default GPIO at reset) with alternate SCI-A transmit, I2C clock SCLA (open-drain) and trip-zone 3 input functions; inputs are not 5-V tolerant. |
| 2 | TRST | input | JTAG test reset with internal pulldown that must be kept low during normal operation, and an external pulldown resistor is required (2.2 kΩ generally offers adequate protection). |
| 3 | XRS | bidirectional | Device reset input and watchdog reset output, open-drain with internal pullup, driven low during power-on/brown-out and for 512 OSCCLK cycles on a watchdog reset; an R-C circuit is recommended for noise immunity. |
| 4 | ADCINA6/AIO6 | passive | ADC Group A channel 6 analog input, or digital analog I/O AIO6 when selected; AIO pins have no internal pullup. |
| 5 | ADCINA4/COMP2A/AIO4 | passive | ADC Group A channel 4 analog input, Comparator 2A input (48-pin device), or digital analog I/O AIO4; AIO pins have no internal pullup. |
| 6 | VSSA | power_in | Analog ground pin. |
| 7 | VSSA | power_in | Analog ground pin. |
| 8 | ADCINA1 | passive | ADC Group A channel 1 analog input. |
| 9 | ADCINA2/COMP1A/AIO2 | passive | ADC Group A channel 2 analog input, Comparator 1A input, or digital analog I/O AIO2; AIO pins have no internal pullup. |
| 10 | VREFHI | input | ADC external high reference, used only in external reference mode, and must not exceed VDDA. |
| 11 | VDDA | power_in | Analog power pin, recommended 2.97 V to 3.63 V (3.3 V nominal), tied with a 2.2-µF (typical) capacitor close to the pin and kept within approximately 0.3 V of VDDIO. |
| 12 | VSSA/VREFLO | power_in | Analog ground pin that doubles as the ADC low reference VREFLO, which is always tied to ground. |
| 13 | ADCINB1 | passive | ADC Group B channel 1 analog input. |
| 14 | ADCINB2/COMP1B/AIO10 | passive | ADC Group B channel 2 analog input, Comparator 1B input, or digital analog I/O AIO10; AIO pins have no internal pullup. |
| 15 | VSSA | power_in | Analog ground pin. |
| 16 | ADCINB4/COMP2B/AIO12 | passive | ADC Group B channel 4 analog input, Comparator 2B input (48-pin device), or digital analog I/O AIO12; AIO pins have no internal pullup. |
| 17 | ADCINB6/AIO14 | passive | ADC Group B channel 6 analog input, or digital analog I/O AIO14; AIO pins have no internal pullup. |
| 18 | VSSA | power_in | Analog ground pin. |
| 19 | GPIO34/COMP2OUT | bidirectional | General-purpose I/O 34 with direct Comparator 2 output COMP2OUT; pin may glitch during power-up when the on-chip VREG is used. |
| 20 | GPIO35 (TDI) | bidirectional | General-purpose I/O 35 with JTAG test data input TDI (internal pullup); pin may glitch during power-up when the on-chip VREG is used. |
| 21 | GPIO36 (TMS) | bidirectional | General-purpose I/O 36 with JTAG test-mode select TMS (internal pullup), clocked into the TAP controller on the rising edge of TCK; pin may glitch during power-up when the on-chip VREG is used. |
| 22 | GPIO37/TDO | bidirectional | General-purpose I/O 37 with JTAG test data output TDO, shifted out on the falling edge of TCK with 8-mA drive; pin may glitch during power-up when the on-chip VREG is used. |
| 23 | GPIO38/XCLKIN (TCK) | bidirectional | General-purpose I/O 38 with JTAG test clock TCK (internal pullup) and external oscillator input XCLKIN; do not enable the XCLKIN clock path while TCK is active during JTAG debug. |
| 24 | GPIO18/SPICLKA/SCITXDA/XCLKOUT | bidirectional | General-purpose I/O 18 with SPI-A clock, SCI-A transmit and XCLKOUT functions; XCLKOUT is SYSCLKOUT, /2 or /4 (SYSCLKOUT/4 at reset) and requires the GPIO18 mux set to XCLKOUT. |
| 25 | GPIO19/XCLKIN/SPISTEA/SCIRXDA/ECAP1 | bidirectional | General-purpose I/O 19 with SPI-A STE, SCI-A receive, ECAP1 and external oscillator input XCLKIN functions; the XCLKIN path is not gated by the pin mux, so it must not be enabled when the pin is used for other peripherals. |
| 26 | GPIO17/SPISOMIA/TZ3 | bidirectional | General-purpose I/O 17 with SPI-A slave-out/master-in and trip-zone 3 input functions. |
| 27 | GPIO16/SPISIMOA/TZ2 | bidirectional | General-purpose I/O 16 with SPI-A slave-in/master-out and trip-zone 2 input functions. |
| 28 | GPIO1/EPWM1B/COMP1OUT | bidirectional | General-purpose I/O 1 with ePWM1B output and direct Comparator 1 output COMP1OUT functions; PWM pin pullups are not enabled at reset. |
| 29 | GPIO0/EPWM1A | bidirectional | General-purpose I/O 0 with ePWM1A output function; PWM pin pullups are not enabled at reset. |
| 30 | TEST | unconnected | Test pin reserved for TI that must be left unconnected. |
| 31 | GPIO32/SDAA/EPWMSYNCI/ADCSOCAO | bidirectional | General-purpose I/O 32 with I2C data SDAA (open-drain), ePWM external sync input and ADC start-of-conversion A output functions. |
| 32 | VDD | power_in | CPU and logic digital power pin; no external supply is needed with the internal VREG, which requires a 1.2-µF minimum ceramic capacitor (10% tolerance) to ground, and 1.71 V to 1.995 V must be supplied externally if VREG is disabled. |
| 33 | VSS | power_in | Digital ground pin. |
| 34 | VREGENZ | input | Internal voltage regulator enable input; pull low to enable the internal VREG and pull high to disable it. |
| 35 | VDDIO | power_in | Digital I/O and flash power pin, 2.97 V to 3.63 V (3.3 V nominal), the single supply source when VREG is enabled, tied with a 2.2-µF (typical) capacitor close to the pin. |
| 36 | GPIO33/SCLA/EPWMSYNCO/ADCSOCBO | bidirectional | General-purpose I/O 33 with I2C clock SCLA (open-drain), ePWM external sync output and ADC start-of-conversion B output functions. |
| 37 | GPIO2/EPWM2A | bidirectional | General-purpose I/O 2 with ePWM2A output function; PWM pin pullups are not enabled at reset. |
| 38 | GPIO3/EPWM2B/COMP2OUT | bidirectional | General-purpose I/O 3 with ePWM2B output and direct Comparator 2 output COMP2OUT (48-pin device) functions. |
| 39 | GPIO4/EPWM3A | bidirectional | General-purpose I/O 4 with ePWM3A output function. |
| 40 | GPIO5/EPWM3B/ECAP1 | bidirectional | General-purpose I/O 5 with ePWM3B output and enhanced capture 1 input/output (ECAP1) functions. |
| 41 | GPIO6/EPWMSYNCI/EPWMSYNCO | bidirectional | General-purpose I/O 6 with ePWM external sync input EPWMSYNCI and sync output EPWMSYNCO functions. |
| 42 | GPIO7/SCIRXDA | bidirectional | General-purpose I/O 7 with SCI-A receive data input function. |
| 43 | VDD | power_in | CPU and logic digital power pin, with the same 1.2-µF minimum ceramic capacitor requirement when the internal VREG is used. |
| 44 | VSS | power_in | Digital ground pin. |
| 45 | X1 | input | On-chip crystal oscillator input; a quartz crystal or ceramic resonator is connected across X1 and X2, and the pin must be tied to GND if not used. |
| 46 | X2 | output | On-chip crystal oscillator output; a quartz crystal or ceramic resonator is connected across X1 and X2, and the pin must be left unconnected if not used. |
| 47 | GPIO12/TZ1/SCITXDA | bidirectional | General-purpose I/O 12 with trip-zone 1 input and SCI-A transmit output functions. |
| 48 | GPIO28/SCIRXDA/SDAA/TZ2 | bidirectional | General-purpose I/O 28 with SCI receive data, I2C data SDAA (open-drain) and trip-zone 2 input functions. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 48 |
CAD (KiCad official)
- Symbol:
TMS320F280230PTT - Footprint:
Package_QFP:LQFP-48_7x7mm_P0.5mm - 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
tms320f280230ptt-etched.step/tms320f280230ptt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tms320f280230ptt.step/tms320f280230ptt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (131 pp, sha256
c31e28b9bb70e614, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).