component
TMS320F28021PTT
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTMS320F28021PTT
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)
TMS320F28021PTT from Texas Instruments, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GPIO29/SCITXDA/SCLA/TZ3 | bidirectional | General-purpose I/O 29 with internal pull-up; alternate functions are SCI-A transmit, I2C-A clock (open-drain) and trip-zone 3 input, and inputs are not 5 V tolerant. |
| 2 | TRST | input | JTAG test reset with internal pull-down; it must be held low during normal operation and an external pull-up (2.2 kΩ typical) is required on this pin. |
| 3 | XRS | bidirectional | Device reset input and watchdog reset output, open-drain with internal pull-up; a 2.2 kΩ to 10 kΩ resistor is to be placed between XRS and VDDIO. |
| 4 | ADCINA6/AIO6 | passive | ADC group A channel 6 analog input, also available as digital AIO6 (AIO pins have no internal pull-up). |
| 5 | ADCINA4/COMP2A/AIO4 | passive | ADC group A channel 4 analog input, also comparator 2A input (available on the 48-pin package only) and digital AIO4. |
| 6 | ADCINA7 | passive | ADC group A channel 7 analog input. |
| 7 | ADCINA3 | passive | ADC group A channel 3 analog input. |
| 8 | ADCINA1 | passive | ADC group A channel 1 analog input. |
| 9 | ADCINA2/COMP1A/AIO2 | passive | ADC group A channel 2 analog input, also comparator 1A input and digital AIO2. |
| 10 | ADCINA0/VREFHI | passive | ADC group A channel 0 analog input; also the ADC external reference high input, used only in ADC external reference mode and not to exceed VDDA. |
| 11 | VDDA | power_in | Analog supply pin; the datasheet recommends 2.97 V to 3.63 V (3.3 V nominal) and a 2.2 µF capacitor (typical) near this pin. |
| 12 | VSSA | power_in | Analog ground pin, also the ADC low reference (VREFLO), which is always tied to ground. |
| 13 | ADCINB1 | passive | ADC group B channel 1 analog input. |
| 14 | ADCINB2/COMP1B/AIO10 | passive | ADC group B channel 2 analog input, also comparator 1B input and digital AIO10. |
| 15 | ADCINB3 | passive | ADC group B channel 3 analog input. |
| 16 | ADCINB4/COMP2B/AIO12 | passive | ADC group B channel 4 analog input, also comparator 2B input (48-pin package only) and digital AIO12. |
| 17 | ADCINB6/AIO14 | passive | ADC group B channel 6 analog input, also digital AIO14. |
| 18 | ADCINB7 | passive | ADC group B channel 7 analog input. |
| 19 | GPIO34/COMP2OUT | bidirectional | General-purpose I/O 34 with internal pull-up; alternate function is the direct output of comparator 2 (48-pin package only). |
| 20 | GPIO35/TDI | bidirectional | General-purpose I/O 35 with internal pull-up; in JTAG mode it is the test data input, sampled on the rising edge of TCK. |
| 21 | GPIO36/TMS | bidirectional | General-purpose I/O 36 with internal pull-up; in JTAG mode it is the test mode select input, sampled on the rising edge of TCK. |
| 22 | GPIO37/TDO | bidirectional | General-purpose I/O 37; in JTAG mode it is the test data output (8 mA drive), shifted out on the falling edge of TCK. |
| 23 | GPIO38/TCK/XCLKIN | bidirectional | General-purpose I/O 38 with internal pull-up; in JTAG mode it is the test clock input, and it is also the default external oscillator input (XCLKIN). |
| 24 | GPIO18/SPICLKA/SCITXDA/XCLKOUT | bidirectional | General-purpose I/O 18 with internal pull-up; alternate functions are SPI-A clock, SCI-A transmit and XCLKOUT (SYSCLKOUT-derived output clock, reset value SYSCLKOUT/4). |
| 25 | GPIO19/XCLKIN/SPISTEA/SCIRXDA/ECAP1 | bidirectional | General-purpose I/O 19 with internal pull-up; alternate functions are external oscillator input XCLKIN, SPI-A slave transmit enable, SCI-A receive and eCAP1; GPIO19 is a power-up glitch source when the internal VREG is used. |
| 26 | GPIO17/SPISOMIA/TZ3 | bidirectional | General-purpose I/O 17 with internal pull-up; alternate functions are SPI-A slave output/master input and trip-zone 3 input; it is in Group 2 for output drive limits (-8 mA/8 mA). |
| 27 | GPIO16/SPISIMOA/TZ2 | bidirectional | General-purpose I/O 16 with internal pull-up; alternate functions are SPI-A slave input/master output and trip-zone 2 input; it is in Group 2 for output drive limits (-8 mA/8 mA). |
| 28 | GPIO1/EPWM1B/COMP1OUT | bidirectional | General-purpose I/O 1 with internal pull-up; alternate functions are ePWM1 output B and the direct output of comparator 1. |
| 29 | GPIO0/EPWM1A | bidirectional | General-purpose I/O 0 with pull-up disabled at reset (PWM pins have no pull-up at reset); alternate function is ePWM1 output A with HRPWM channel. |
| 30 | TEST | bidirectional | Reserved for TI; this I/O pin must be left unconnected. |
| 31 | GPIO32/SDAA/EPWMSYNCI/ADCSOCAO | bidirectional | General-purpose I/O 32; alternate functions are I2C-A data (open-drain), ePWM external sync input and ADC start-of-conversion A output. |
| 32 | VDD | power_in | CPU and logic digital supply; when using the internal VREG, place a 1.2 µF capacitor (minimum) between each VDD pin and ground, and the recommended VDD supply is 1.71 V to 1.995 V when the VREG is disabled. |
| 33 | VSS | power_in | Digital ground pin. |
| 34 | VREGENZ | input | Internal regulator enable with internal pull-down; tie to VSS to enable the internal 1.8 V VREG, or to VDDIO to disable it and use an external 1.8 V supply. |
| 35 | VDDIO | power_in | Digital I/O buffer and flash supply, recommended 2.97 V to 3.63 V (3.3 V nominal); a decoupling capacitor is to be placed on this pin. |
| 36 | GPIO33/SCLA/EPWMSYNCO/ADCSOCBO | bidirectional | General-purpose I/O 33; alternate functions are I2C-A clock (open-drain), ePWM external sync output and ADC start-of-conversion B output. |
| 37 | GPIO2/EPWM2A | bidirectional | General-purpose I/O 2 with pull-up disabled at reset; alternate function is ePWM2 output A with HRPWM channel. |
| 38 | GPIO3/EPWM2B/COMP2OUT | bidirectional | General-purpose I/O 3 with pull-up disabled at reset; alternate functions are ePWM2 output B and comparator 2 direct output (48-pin package only). |
| 39 | GPIO4/EPWM3A | bidirectional | General-purpose I/O 4 with pull-up disabled at reset; alternate function is ePWM3 output A with HRPWM channel. |
| 40 | GPIO5/EPWM3B/ECAP1 | bidirectional | General-purpose I/O 5 with pull-up disabled at reset; alternate functions are ePWM3 output B and enhanced capture I/O 1. |
| 41 | GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO | bidirectional | General-purpose I/O 6 with pull-up disabled at reset; alternate functions are ePWM4 output A with HRPWM channel, external ePWM sync input and external ePWM sync output. |
| 42 | GPIO7/EPWM4B/SCIRXDA | bidirectional | General-purpose I/O 7 with pull-up disabled at reset; alternate functions are ePWM4 output B and SCI-A receive data. |
| 43 | VDD | power_in | CPU and logic digital supply; when using the internal VREG, place a 1.2 µF capacitor (minimum) between each VDD pin and ground. |
| 44 | VSS | power_in | Digital ground pin. |
| 45 | X1 | input | 1.8 V on-chip crystal oscillator input; it must never receive 3.3 V signals and must be connected to GND if not used. |
| 46 | X2 | output | On-chip crystal oscillator output; a quartz crystal or ceramic resonator must be connected between X1 and X2, and X2 must be left unconnected if not used. |
| 47 | GPIO12/TZ1/SCITXDA | bidirectional | General-purpose I/O 12 with internal pull-up; alternate functions are trip-zone 1 input and SCI-A transmit data. |
| 48 | GPIO28/SCIRXDA/SDAA/TZ2 | bidirectional | General-purpose I/O 28 with internal pull-up; alternate functions are SCI receive data, I2C-A data (open-drain) and trip-zone 2 input; it is in Group 2 for output drive limits (-8 mA/8 mA). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 48 |
CAD (KiCad official)
- Symbol:
TMS320F28021PTT - Footprint:
Package_QFP:LQFP-48_7x7mm_P0.5mm - 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
tms320f28021ptt-etched.step/tms320f28021ptt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tms320f28021ptt.step/tms320f28021ptt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (147 pp, sha256
b90c388f4142c4b5, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).