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TMS320F28021PTS

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TMS320F28021PTS

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

TMS320F28021PTS from Texas Instruments, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO29/SCITXDA/SCLA/TZ3 bidirectional General-purpose I/O (I/O/Z, not 5 V tolerant) with selectable internal pullup; alternates are SCI-A transmit, I2C-A clock (open-drain) and trip-zone input TZ3.
2 TRST input JTAG test reset with internal pulldown; must be held low during normal operation, and an external pullup (about 2.2 kΩ typical) is required on this pin.
3 XRS bidirectional Open-drain device reset input and watchdog reset output with internal pullup; a 2.2 kΩ to 10 kΩ resistor to VDDIO is recommended and any noise-filter capacitor to VSS should be 100 nF or less.
4 ADCINA6/AIO6 bidirectional ADC group A channel 6 analog input, also usable as digital AIO6 I/O (AIO pins have no internal pullup).
5 ADCINA4/COMP2A/AIO4 bidirectional ADC group A channel 4 analog input, also comparator 2A input (48-pin device only) and digital AIO4 I/O.
6 ADCINA7 input ADC group A channel 7 analog input.
7 ADCINA3 input ADC group A channel 3 analog input.
8 ADCINA1 input ADC group A channel 1 analog input.
9 ADCINA2/COMP1A/AIO2 bidirectional ADC group A channel 2 analog input, also comparator 1A input and digital AIO2 I/O.
10 ADCINA0/VREFHI input ADC group A channel 0 analog input; used as external ADC reference high only in external reference mode, and VREFHI must not exceed VDDA.
11 VDDA power_in Analog supply, 2.97 V to 3.63 V (3.3 V nominal); place a 2.2 µF capacitor (typical) near this pin.
12 VSSA/VREFLO power_in Analog ground; also the ADC external reference low (VREFLO), which is always grounded.
13 ADCINB1 input ADC group B channel 1 analog input.
14 ADCINB2/COMP1B/AIO10 bidirectional ADC group B channel 2 analog input, also comparator 1B input and digital AIO10 I/O.
15 ADCINB3 input ADC group B channel 3 analog input.
16 ADCINB4/COMP2B/AIO12 bidirectional ADC group B channel 4 analog input, also comparator 2B input (48-pin device only) and digital AIO12 I/O.
17 ADCINB6/AIO14 bidirectional ADC group B channel 6 analog input, also usable as digital AIO14 I/O.
18 ADCINB7 input ADC group B channel 7 analog input.
19 GPIO34/COMP2OUT bidirectional General-purpose I/O (I/O/Z, not 5 V tolerant); alternate is the direct output of comparator 2 (48-pin device only); may glitch at power-up when the internal VREG is used.
20 GPIO35/TDI bidirectional General-purpose I/O (I/O/Z, not 5 V tolerant); JTAG test data input TDI with internal pullup, sampled on the rising edge of TCK, and may glitch at power-up when the internal VREG is used.
21 GPIO36/TMS bidirectional General-purpose I/O (I/O/Z, not 5 V tolerant); JTAG test mode select TMS with internal pullup, sampled on the rising edge of TCK, and may glitch at power-up when the internal VREG is used.
22 GPIO37/TDO tri_state General-purpose I/O (I/O/Z); JTAG test data output TDO with 8 mA drive, shifted out on the falling edge of TCK, and may glitch at power-up when the internal VREG is used.
23 GPIO38/XCLKIN/TCK bidirectional General-purpose I/O (I/O/Z); JTAG test clock TCK with internal pullup, and alternate external oscillator input XCLKIN (the XCLKIN path must be disabled for crystal operation or during JTAG debug).
24 GPIO18/SPICLKA/SCITXDA/XCLKOUT bidirectional General-purpose I/O (I/O/Z, group 2 pin); alternates are SPI-A clock, SCI-A transmit and XCLKOUT derived from SYSCLKOUT (reset default SYSCLKOUT/4).
25 GPIO19/XCLKIN/SPISTEA/SCIRXDA/ECAP1 bidirectional General-purpose I/O (I/O/Z, group 2 pin); alternates are external oscillator input XCLKIN, SPI-A slave transmit enable, SCI-A receive and eCAP1 I/O, and may glitch at power-up when the internal VREG is used.
26 GPIO17/SPISOMIA/TZ3 bidirectional General-purpose I/O (I/O/Z, group 2 pin); alternates are SPI-A slave output/master input and trip-zone input TZ3, and may glitch at power-up when the internal VREG is used.
27 GPIO16/SPISIMOA/TZ2 bidirectional General-purpose I/O (I/O/Z, group 2 pin); alternates are SPI-A slave input/master output and trip-zone input TZ2.
28 GPIO1/EPWM1B/COMP1OUT bidirectional General-purpose I/O (I/O/Z); alternates are ePWM1 output B (no internal pullup at reset for PWM pins) and direct output of comparator 1.
29 GPIO0/EPWM1A bidirectional General-purpose I/O (I/O/Z); alternate is ePWM1 output A with HRPWM channel (no internal pullup at reset for PWM pins).
30 TEST bidirectional Reserved for TI; must remain unconnected.
31 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO bidirectional General-purpose I/O (I/O/Z); alternates are I2C-A data (open-drain), ePWM external sync input and ADC start-of-conversion A output.
32 VDD power_in CPU and logic digital supply; when the internal VREG is used, place a 1.2 µF (minimum) capacitor between each VDD pin and ground, and when VREG is disabled it is supplied externally at 1.71 V to 1.995 V (1.8 V nominal).
33 VSS power_in Digital ground.
34 VREGENZ input Internal regulator enable with internal pulldown; tie low (VSS) to enable the internal 1.8 V VREG, or tie high (VDDIO) to disable it and use an external 1.8 V VDD supply.
35 VDDIO power_in Digital I/O buffer and flash supply, 2.97 V to 3.63 V (3.3 V nominal); a decoupling capacitor should be placed on this pin.
36 GPIO33/SCLA/EPWMSYNCO/ADCSOCBO bidirectional General-purpose I/O (I/O/Z); alternates are I2C-A clock (open-drain), ePWM external sync output and ADC start-of-conversion B output.
37 GPIO2/EPWM2A bidirectional General-purpose I/O (I/O/Z); alternate is ePWM2 output A with HRPWM channel (no internal pullup at reset for PWM pins).
38 GPIO3/EPWM2B/COMP2OUT bidirectional General-purpose I/O (I/O/Z); alternates are ePWM2 output B and direct output of comparator 2 (48-pin device only).
39 GPIO4/EPWM3A bidirectional General-purpose I/O (I/O/Z); alternate is ePWM3 output A with HRPWM channel (no internal pullup at reset for PWM pins).
40 GPIO5/EPWM3B/ECAP1 bidirectional General-purpose I/O (I/O/Z); alternates are ePWM3 output B and enhanced capture input/output 1.
41 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO bidirectional General-purpose I/O (I/O/Z); alternates are ePWM4 output A with HRPWM channel, ePWM external sync input and ePWM external sync output.
42 GPIO7/EPWM4B/SCIRXDA bidirectional General-purpose I/O (I/O/Z); alternates are ePWM4 output B and SCI-A receive data.
43 VDD power_in CPU and logic digital supply; when the internal VREG is used, place a 1.2 µF (minimum) capacitor between each VDD pin and ground.
44 VSS power_in Digital ground.
45 X1 input 1.8 V on-chip crystal oscillator input; a crystal or ceramic resonator must be connected between X1 and X2, and the pin must be tied to GND if the oscillator is unused.
46 X2 output On-chip crystal oscillator output; connect a crystal or ceramic resonator between X1 and X2, and leave unconnected if X2 is unused.
47 GPIO12/TZ1/SCITXDA bidirectional General-purpose I/O (I/O/Z); alternates are trip-zone input TZ1 and SCI-A transmit data.
48 GPIO28/SCIRXDA/SDAA/TZ2 bidirectional General-purpose I/O (I/O/Z, group 2 pin); alternates are SCI receive data, I2C-A data (open-drain) and trip-zone input TZ2.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

CAD (KiCad official)

  • Symbol: TMS320F28021PTS
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: tms320f28021pts-etched.step / tms320f28021pts-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f28021pts.step / tms320f28021pts.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (147 pp, sha256 b90c388f4142c4b5, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF