component
TMS320F28020PTT
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+85@@ -0,0 +1,85 @@+# TMS320F28020PTT++**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)++TMS320F28020PTT from Texas Instruments, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GPIO29/SCITXDA/SCLA/TZ3 | bidirectional | General-purpose I/O 29 with alternate functions SCI-A transmit (SCITXDA), I2C-A clock open-drain (SCLA) and trip-zone input TZ3. |+| 2 | TRST | input | JTAG test reset with internal pull-down; it must be held low during normal operation and needs an external pull-up (2.2 kΩ is typically sufficient, depending on the debug probe). |+| 3 | XRS | bidirectional | Open-drain device reset input and watchdog reset output with internal pull-up; it is driven low on power-up/brown-out and during watchdog reset, and needs a 2.2 kΩ to 10 kΩ resistor to VDDIO. |+| 4 | ADCINA6/AIO6 | passive | ADC group A channel 6 analog input, also selectable as digital AIO6; unused ADC inputs should be tied to VSSA (or through 1 kΩ if shared with AIO). |+| 5 | ADCINA4/COMP2A/AIO4 | passive | ADC group A channel 4 analog input, also comparator 2A input (48-pin device only) and AIO4. |+| 6 | ADCINA7 | passive | ADC group A channel 7 analog input. |+| 7 | ADCINA3 | passive | ADC group A channel 3 analog input. |+| 8 | ADCINA1 | passive | ADC group A channel 1 analog input. |+| 9 | ADCINA2/COMP1A/AIO2 | passive | ADC group A channel 2 analog input, also comparator 1A input and AIO2. |+| 10 | ADCINA0/VREFHI | passive | ADC group A channel 0 analog input; VREFHI is the external ADC high reference used only in external reference mode and must not exceed VDDA. |+| 11 | VDDA | power_in | Analog supply pin (2.97 V to 3.63 V, 3.3 V nominal) with a 2.2 µF capacitor (typical) placed near the pin. |+| 12 | VSSA/VREFLO | power_in | Analog ground, which also serves as the ADC external low reference VREFLO and is always grounded. |+| 13 | ADCINB1 | passive | ADC group B channel 1 analog input. |+| 14 | ADCINB2/COMP1B/AIO10 | passive | ADC group B channel 2 analog input, also comparator 1B input and AIO10. |+| 15 | ADCINB3 | passive | ADC group B channel 3 analog input. |+| 16 | ADCINB4/COMP2B/AIO12 | passive | ADC group B channel 4 analog input, also comparator 2B input (48-pin device only) and AIO12. |+| 17 | ADCINB6/AIO14 | passive | ADC group B channel 6 analog input, also selectable as digital AIO14. |+| 18 | ADCINB7 | passive | ADC group B channel 7 analog input. |+| 19 | GPIO34/COMP2OUT | bidirectional | General-purpose I/O 34 with direct comparator 2 output COMP2OUT (48-pin device only); it may glitch during power-up when the on-chip VREG is used. |+| 20 | GPIO35/TDI | bidirectional | General-purpose I/O 35 with JTAG test data input TDI (internal pull-up), sampled on the TCK rising edge; it may glitch during power-up when the on-chip VREG is used. |+| 21 | GPIO36/TMS | bidirectional | General-purpose I/O 36 with JTAG test mode select TMS (internal pull-up), sampled on the TCK rising edge; it may glitch during power-up when the on-chip VREG is used. |+| 22 | GPIO37/TDO | tri_state | General-purpose I/O 37 with JTAG test data output TDO (8 mA drive), shifted out on the TCK falling edge; it may glitch during power-up when the on-chip VREG is used. |+| 23 | GPIO38/XCLKIN/TCK | bidirectional | General-purpose I/O 38 with JTAG test clock TCK (internal pull-up) and the default external oscillator input XCLKIN; an alternate clock source is needed during JTAG debug if this pin is used for XCLKIN. |+| 24 | GPIO18/SPICLKA/SCITXDA/XCLKOUT | bidirectional | General-purpose I/O 18 with SPI-A clock, SCI-A transmit and XCLKOUT output (SYSCLKOUT/4 at reset); it is a group 2 pin limited to IOH -8 mA and IOL 8 mA. |+| 25 | GPIO19/XCLKIN/SPISTEA/SCIRXDA/ECAP1 | bidirectional | General-purpose I/O 19 with external oscillator input XCLKIN, SPI-A slave transmit enable, SCI-A receive and eCAP1; it is a group 2 pin and may glitch during power-up when the on-chip VREG is used. |+| 26 | GPIO17/SPISOMIA/TZ3 | bidirectional | General-purpose I/O 17 with SPI-A slave output/master input (SPISOMIA) and trip-zone input TZ3; it is a group 2 pin. |+| 27 | GPIO16/SPISIMOA/TZ2 | bidirectional | General-purpose I/O 16 with SPI-A slave input/master output (SPISIMOA) and trip-zone input TZ2; it is a group 2 pin. |+| 28 | GPIO1/EPWM1B/COMP1OUT | bidirectional | General-purpose I/O 1 with ePWM1B output and direct comparator 1 output COMP1OUT. |+| 29 | GPIO0/EPWM1A | bidirectional | General-purpose I/O 0 with ePWM1A output and HRPWM channel; PWM pins have their pull-ups disabled at reset. |+| 30 | TEST | bidirectional | Reserved for TI; it must be left unconnected. |+| 31 | GPIO32/SDAA/EPWMSYNCI/ADCSOCAO | bidirectional | General-purpose I/O 32 with I2C-A data open-drain (SDAA), ePWM external sync input (EPWMSYNCI) and ADC start-of-conversion A output (ADCSOCAO). |+| 32 | VDD | power_in | CPU and logic core supply; with the internal VREG in use, place a 1.2 µF (minimum) capacitor on each VDD pin, or supply 1.71 V to 1.995 V externally when VREG is disabled. |+| 33 | VSS | power_in | Digital ground pin. |+| 34 | VREGENZ | input | Internal voltage regulator enable with internal pull-down: tie to VSS to enable the internal 1.8 V VREG, or tie to VDDIO to disable it and supply 1.8 V externally on VDD. |+| 35 | VDDIO | power_in | Digital I/O and Flash supply (2.97 V to 3.63 V, 3.3 V nominal) that also supplies the VREG when enabled; place a decoupling capacitor on this pin. |+| 36 | GPIO33/SCLA/EPWMSYNCO/ADCSOCBO | bidirectional | General-purpose I/O 33 with I2C-A clock open-drain (SCLA), ePWM external sync output (EPWMSYNCO) and ADC start-of-conversion B output (ADCSOCBO). |+| 37 | GPIO2/EPWM2A | bidirectional | General-purpose I/O 2 with ePWM2A output and HRPWM channel. |+| 38 | GPIO3/EPWM2B/COMP2OUT | bidirectional | General-purpose I/O 3 with ePWM2B output and direct comparator 2 output COMP2OUT (48-pin device only). |+| 39 | GPIO4/EPWM3A | bidirectional | General-purpose I/O 4 with ePWM3A output and HRPWM channel. |+| 40 | GPIO5/EPWM3B/ECAP1 | bidirectional | General-purpose I/O 5 with ePWM3B output and enhanced capture I/O 1 (ECAP1). |+| 41 | GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO | bidirectional | General-purpose I/O 6 with ePWM4A output and HRPWM channel, plus external ePWM sync input (EPWMSYNCI) and sync output (EPWMSYNCO). |+| 42 | GPIO7/EPWM4B/SCIRXDA | bidirectional | General-purpose I/O 7 with ePWM4B output and SCI-A receive data (SCIRXDA). |+| 43 | VDD | power_in | CPU and logic core supply; with the internal VREG in use, place a 1.2 µF (minimum) capacitor on each VDD pin. |+| 44 | VSS | power_in | Digital ground pin. |+| 45 | X1 | input | 1.8 V on-chip crystal oscillator input that must never receive 3.3 V signals; connect a crystal or resonator between X1 and X2, or tie to GND if unused. |+| 46 | X2 | output | On-chip crystal oscillator output that must be connected to a crystal or resonator with X1, or left unconnected if unused. |+| 47 | GPIO12/TZ1/SCITXDA | bidirectional | General-purpose I/O 12 with trip-zone input TZ1 and SCI-A transmit (SCITXDA). |+| 48 | GPIO28/SCIRXDA/SDAA/TZ2 | bidirectional | General-purpose I/O 28 with SCI receive data (SCIRXDA), I2C-A data open-drain (SDAA) and trip-zone input TZ2; it is a group 2 pin. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | LQFP-48(7x7) |+| Category | Embedded Processors & Controllers |+| Pins | 48 |++## CAD (KiCad official)++- Symbol: `TMS320F28020PTT`+- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`+- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)+- 3D model files: `tms320f28020ptt-etched.step` / `tms320f28020ptt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tms320f28020ptt.step` / `tms320f28020ptt.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tms320f28020) (147 pp, sha256 `b90c388f4142c4b5`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tms320f28020ptt-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "tms320f28020ptt",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tms320f28020ptt.kicad_sym",+ "tms320f28020ptt.kicad_mod",+ "tms320f28020ptt.glb",+ "tms320f28020ptt.step",+ "tms320f28020ptt.lbr",+ "docs/hero.png",+ "docs/tms320f28020ptt-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tms320f28020ptt-hero.glb",+ "tms320f28020ptt-hero.overlay.json"+ ],+ "component": {+ "mpn": "TMS320F28020PTT",+ "manufacturer": "Texas Instruments",+ "package": "LQFP-48(7x7)",+ "pin_count": 48,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tms320f28020",+ "parts": {+ "symbol": "tms320f28020ptt.kicad_sym",+ "footprint": "tms320f28020ptt.kicad_mod",+ "model_3d": "tms320f28020ptt-hero.glb",+ "model_3d_plain": "tms320f28020ptt.glb",+ "model_3d_step": "tms320f28020ptt-etched.step",+ "model_3d_step_plain": "tms320f28020ptt.step",+ "lbr": "tms320f28020ptt.lbr"+ },+ "distributor_links": {+ "lcsc": "C1339390",+ "digikey": "296-27539-ND",+ "mouser": "595-TMS320F28020PTT"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T01:17:01Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-27539-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-TMS320F28020PTT",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "GPIO29/SCITXDA/SCLA/TZ3",+ "type": "bidirectional",+ "description": "General-purpose I/O 29 with alternate functions SCI-A transmit (SCITXDA), I2C-A clock open-drain (SCLA) and trip-zone input TZ3."+ },+ {+ "number": "2",+ "name": "TRST",+ "type": "input",+ "description": "JTAG test reset with internal pull-down; it must be held low during normal operation and needs an external pull-up (2.2 kΩ is typically sufficient, depending on the debug probe)."+ },+ {+ "number": "3",+ "name": "XRS",+ "type": "bidirectional",+ "description": "Open-drain device reset input and watchdog reset output with internal pull-up; it is driven low on power-up/brown-out and during watchdog reset, and needs a 2.2 kΩ to 10 kΩ resistor to VDDIO."+ },+ {+ "number": "4",+ "name": "ADCINA6/AIO6",+ "type": "passive",+ "description": "ADC group A channel 6 analog input, also selectable as digital AIO6; unused ADC inputs should be tied to VSSA (or through 1 kΩ if shared with AIO)."+ },+ {+ "number": "5",+ "name": "ADCINA4/COMP2A/AIO4",+ "type": "passive",+ "description": "ADC group A channel 4 analog input, also comparator 2A input (48-pin device only) and AIO4."+ },+ {+ "number": "6",+ "name": "ADCINA7",+ "type": "passive",+ "description": "ADC group A channel 7 analog input."+ },+ {+ "number": "7",+ "name": "ADCINA3",+ "type": "passive",+ "description": "ADC group A channel 3 analog input."+ },+ {+ "number": "8",+ "name": "ADCINA1",+ "type": "passive",+ "description": "ADC group A channel 1 analog input."+ },+ {+ "number": "9",+ "name": "ADCINA2/COMP1A/AIO2",+ "type": "passive",+ "description": "ADC group A channel 2 analog input, also comparator 1A input and AIO2."+ },+ {+ "number": "10",+ "name": "ADCINA0/VREFHI",+ "type": "passive",+ "description": "ADC group A channel 0 analog input; VREFHI is the external ADC high reference used only in external reference mode and must not exceed VDDA."+ },+ {+ "number": "11",+ "name": "VDDA",+ "type": "power_in",+ "description": "Analog supply pin (2.97 V to 3.63 V, 3.3 V nominal) with a 2.2 µF capacitor (typical) placed near the pin."+ },+ {+ "number": "12",+ "name": "VSSA/VREFLO",+ "type": "power_in",+ "description": "Analog ground, which also serves as the ADC external low reference VREFLO and is always grounded."+ },+ {+ "number": "13",+ "name": "ADCINB1",+ "type": "passive",+ "description": "ADC group B channel 1 analog input."+ },+ {+ "number": "14",+ "name": "ADCINB2/COMP1B/AIO10",+ "type": "passive",+ "description": "ADC group B channel 2 analog input, also comparator 1B input and AIO10."+ },+ {+ "number": "15",+ "name": "ADCINB3",+ "type": "passive",+ "description": "ADC group B channel 3 analog input."+ },+ {+ "number": "16",+ "name": "ADCINB4/COMP2B/AIO12",+ "type": "passive",+ "description": "ADC group B channel 4 analog input, also comparator 2B input (48-pin device only) and AIO12."+ },+ {+ "number": "17",+ "name": "ADCINB6/AIO14",+ "type": "passive",+ "description": "ADC group B channel 6 analog input, also selectable as digital AIO14."+ },+ {+ "number": "18",+ "name": "ADCINB7",+ "type": "passive",+ "description": "ADC group B channel 7 analog input."+ },+ {+ "number": "19",+ "name": "GPIO34/COMP2OUT",+ "type": "bidirectional",+ "description": "General-purpose I/O 34 with direct comparator 2 output COMP2OUT (48-pin device only); it may glitch during power-up when the on-chip VREG is used."+ },+ {+ "number": "20",+ "name": "GPIO35/TDI",+ "type": "bidirectional",+ "description": "General-purpose I/O 35 with JTAG test data input TDI (internal pull-up), sampled on the TCK rising edge; it may glitch during power-up when the on-chip VREG is used."+ },+ {+ "number": "21",+ "name": "GPIO36/TMS",+ "type": "bidirectional",+ "description": "General-purpose I/O 36 with JTAG test mode select TMS (internal pull-up), sampled on the TCK rising edge; it may glitch during power-up when the on-chip VREG is used."+ },+ {+ "number": "22",+ "name": "GPIO37/TDO",+ "type": "tri_state",+ "description": "General-purpose I/O 37 with JTAG test data output TDO (8 mA drive), shifted out on the TCK falling edge; it may glitch during power-up when the on-chip VREG is used."+ },+ {+ "number": "23",+ "name": "GPIO38/XCLKIN/TCK",+ "type": "bidirectional",+ "description": "General-purpose I/O 38 with JTAG test clock TCK (internal pull-up) and the default external oscillator input XCLKIN; an alternate clock source is needed during JTAG debug if this pin is used for XCLKIN."+ },+ {+ "number": "24",+ "name": "GPIO18/SPICLKA/SCITXDA/XCLKOUT",+ "type": "bidirectional",+ "description": "General-purpose I/O 18 with SPI-A clock, SCI-A transmit and XCLKOUT output (SYSCLKOUT/4 at reset); it is a group 2 pin limited to IOH -8 mA and IOL 8 mA."+ },+ {+ "number": "25",+ "name": "GPIO19/XCLKIN/SPISTEA/SCIRXDA/ECAP1",+ "type": "bidirectional",+ "description": "General-purpose I/O 19 with external oscillator input XCLKIN, SPI-A slave transmit enable, SCI-A receive and eCAP1; it is a group 2 pin and may glitch during power-up when the on-chip VREG is used."+ },+ {+ "number": "26",+ "name": "GPIO17/SPISOMIA/TZ3",+ "type": "bidirectional",+ "description": "General-purpose I/O 17 with SPI-A slave output/master input (SPISOMIA) and trip-zone input TZ3; it is a group 2 pin."+ },+ {+ "number": "27",+ "name": "GPIO16/SPISIMOA/TZ2",+ "type": "bidirectional",+ "description": "General-purpose I/O 16 with SPI-A slave input/master output (SPISIMOA) and trip-zone input TZ2; it is a group 2 pin."+ },+ {+ "number": "28",+ "name": "GPIO1/EPWM1B/COMP1OUT",+ "type": "bidirectional",+ "description": "General-purpose I/O 1 with ePWM1B output and direct comparator 1 output COMP1OUT."+ },+ {+ "number": "29",+ "name": "GPIO0/EPWM1A",+ "type": "bidirectional",+ "description": "General-purpose I/O 0 with ePWM1A output and HRPWM channel; PWM pins have their pull-ups disabled at reset."+ },+ {+ "number": "30",+ "name": "TEST",+ "type": "bidirectional",+ "description": "Reserved for TI; it must be left unconnected."+ },+ {+ "number": "31",+ "name": "GPIO32/SDAA/EPWMSYNCI/ADCSOCAO",+ "type": "bidirectional",+ "description": "General-purpose I/O 32 with I2C-A data open-drain (SDAA), ePWM external sync input (EPWMSYNCI) and ADC start-of-conversion A output (ADCSOCAO)."+ },+ {+ "number": "32",+ "name": "VDD",+ "type": "power_in",+ "description": "CPU and logic core supply; with the internal VREG in use, place a 1.2 µF (minimum) capacitor on each VDD pin, or supply 1.71 V to 1.995 V externally when VREG is disabled."+ },+ {+ "number": "33",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin."+ },+ {+ "number": "34",+ "name": "VREGENZ",+ "type": "input",+ "description": "Internal voltage regulator enable with internal pull-down: tie to VSS to enable the internal 1.8 V VREG, or tie to VDDIO to disable it and supply 1.8 V externally on VDD."+ },+ {+ "number": "35",+ "name": "VDDIO",+ "type": "power_in",+ "description": "Digital I/O and Flash supply (2.97 V to 3.63 V, 3.3 V nominal) that also supplies the VREG when enabled; place a decoupling capacitor on this pin."+ },+ {+ "number": "36",+ "name": "GPIO33/SCLA/EPWMSYNCO/ADCSOCBO",+ "type": "bidirectional",+ "description": "General-purpose I/O 33 with I2C-A clock open-drain (SCLA), ePWM external sync output (EPWMSYNCO) and ADC start-of-conversion B output (ADCSOCBO)."+ },+ {+ "number": "37",+ "name": "GPIO2/EPWM2A",+ "type": "bidirectional",+ "description": "General-purpose I/O 2 with ePWM2A output and HRPWM channel."+ },+ {+ "number": "38",+ "name": "GPIO3/EPWM2B/COMP2OUT",+ "type": "bidirectional",+ "description": "General-purpose I/O 3 with ePWM2B output and direct comparator 2 output COMP2OUT (48-pin device only)."+ },+ {+ "number": "39",+ "name": "GPIO4/EPWM3A",+ "type": "bidirectional",+ "description": "General-purpose I/O 4 with ePWM3A output and HRPWM channel."+ },+ {+ "number": "40",+ "name": "GPIO5/EPWM3B/ECAP1",+ "type": "bidirectional",+ "description": "General-purpose I/O 5 with ePWM3B output and enhanced capture I/O 1 (ECAP1)."+ },+ {+ "number": "41",+ "name": "GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO",+ "type": "bidirectional",+ "description": "General-purpose I/O 6 with ePWM4A output and HRPWM channel, plus external ePWM sync input (EPWMSYNCI) and sync output (EPWMSYNCO)."+ },+ {+ "number": "42",+ "name": "GPIO7/EPWM4B/SCIRXDA",+ "type": "bidirectional",+ "description": "General-purpose I/O 7 with ePWM4B output and SCI-A receive data (SCIRXDA)."+ },+ {+ "number": "43",+ "name": "VDD",+ "type": "power_in",+ "description": "CPU and logic core supply; with the internal VREG in use, place a 1.2 µF (minimum) capacitor on each VDD pin."+ },+ {+ "number": "44",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground pin."+ },+ {+ "number": "45",+ "name": "X1",+ "type": "input",+ "description": "1.8 V on-chip crystal oscillator input that must never receive 3.3 V signals; connect a crystal or resonator between X1 and X2, or tie to GND if unused."+ },+ {+ "number": "46",+ "name": "X2",+ "type": "output",+ "description": "On-chip crystal oscillator output that must be connected to a crystal or resonator with X1, or left unconnected if unused."+ },+ {+ "number": "47",+ "name": "GPIO12/TZ1/SCITXDA",+ "type": "bidirectional",+ "description": "General-purpose I/O 12 with trip-zone input TZ1 and SCI-A transmit (SCITXDA)."+ },+ {+ "number": "48",+ "name": "GPIO28/SCIRXDA/SDAA/TZ2",+ "type": "bidirectional",+ "description": "General-purpose I/O 28 with SCI receive data (SCIRXDA), I2C-A data open-drain (SDAA) and trip-zone input TZ2; it is a group 2 pin."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Figure 7-1 (page 8) text extraction is garbled around pins 2-3 and the GPIO12 label. Pin assignments; The datasheet covers the whole F2802x family. The 48-pin PT pinout in Table 7.2.1 is shared by TMS32; TEST (pin 30) is typed I/O in the datasheet but must be left unconnected. It was typed bidirectional"+ ],+ "pages_sent": 85,+ "cost_usd": 0.6088,+ "at": "2026-10-08T01:16:37"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tms320f28020",+ "pages": 147,+ "sha256": "b90c388f4142c4b5",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 48,+ "described": 48,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tms320f28020ptt.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "9dea352d93177c2904afd7d7b68ea8855ce1ab691f69f8b3e13655600514b6bf",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tms320f28020ptt-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "d20b908019f5c5d517dbb834826ae6e87551037268b4d95e7433379dad0e352c",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}