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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

TMS320F28020PTT

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

TMS320F28020PTT from Texas Instruments, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GPIO29/SCITXDA/SCLA/TZ3	bidirectional	General-purpose I/O 29 with alternate functions SCI-A transmit (SCITXDA), I2C-A clock open-drain (SCLA) and trip-zone input TZ3.
2	TRST	input	JTAG test reset with internal pull-down; it must be held low during normal operation and needs an external pull-up (2.2 kΩ is typically sufficient, depending on the debug probe).
3	XRS	bidirectional	Open-drain device reset input and watchdog reset output with internal pull-up; it is driven low on power-up/brown-out and during watchdog reset, and needs a 2.2 kΩ to 10 kΩ resistor to VDDIO.
4	ADCINA6/AIO6	passive	ADC group A channel 6 analog input, also selectable as digital AIO6; unused ADC inputs should be tied to VSSA (or through 1 kΩ if shared with AIO).
5	ADCINA4/COMP2A/AIO4	passive	ADC group A channel 4 analog input, also comparator 2A input (48-pin device only) and AIO4.
6	ADCINA7	passive	ADC group A channel 7 analog input.
7	ADCINA3	passive	ADC group A channel 3 analog input.
8	ADCINA1	passive	ADC group A channel 1 analog input.
9	ADCINA2/COMP1A/AIO2	passive	ADC group A channel 2 analog input, also comparator 1A input and AIO2.
10	ADCINA0/VREFHI	passive	ADC group A channel 0 analog input; VREFHI is the external ADC high reference used only in external reference mode and must not exceed VDDA.
11	VDDA	power_in	Analog supply pin (2.97 V to 3.63 V, 3.3 V nominal) with a 2.2 µF capacitor (typical) placed near the pin.
12	VSSA/VREFLO	power_in	Analog ground, which also serves as the ADC external low reference VREFLO and is always grounded.
13	ADCINB1	passive	ADC group B channel 1 analog input.
14	ADCINB2/COMP1B/AIO10	passive	ADC group B channel 2 analog input, also comparator 1B input and AIO10.
15	ADCINB3	passive	ADC group B channel 3 analog input.
16	ADCINB4/COMP2B/AIO12	passive	ADC group B channel 4 analog input, also comparator 2B input (48-pin device only) and AIO12.
17	ADCINB6/AIO14	passive	ADC group B channel 6 analog input, also selectable as digital AIO14.
18	ADCINB7	passive	ADC group B channel 7 analog input.
19	GPIO34/COMP2OUT	bidirectional	General-purpose I/O 34 with direct comparator 2 output COMP2OUT (48-pin device only); it may glitch during power-up when the on-chip VREG is used.
20	GPIO35/TDI	bidirectional	General-purpose I/O 35 with JTAG test data input TDI (internal pull-up), sampled on the TCK rising edge; it may glitch during power-up when the on-chip VREG is used.
21	GPIO36/TMS	bidirectional	General-purpose I/O 36 with JTAG test mode select TMS (internal pull-up), sampled on the TCK rising edge; it may glitch during power-up when the on-chip VREG is used.
22	GPIO37/TDO	tri_state	General-purpose I/O 37 with JTAG test data output TDO (8 mA drive), shifted out on the TCK falling edge; it may glitch during power-up when the on-chip VREG is used.
23	GPIO38/XCLKIN/TCK	bidirectional	General-purpose I/O 38 with JTAG test clock TCK (internal pull-up) and the default external oscillator input XCLKIN; an alternate clock source is needed during JTAG debug if this pin is used for XCLKIN.
24	GPIO18/SPICLKA/SCITXDA/XCLKOUT	bidirectional	General-purpose I/O 18 with SPI-A clock, SCI-A transmit and XCLKOUT output (SYSCLKOUT/4 at reset); it is a group 2 pin limited to IOH -8 mA and IOL 8 mA.
25	GPIO19/XCLKIN/SPISTEA/SCIRXDA/ECAP1	bidirectional	General-purpose I/O 19 with external oscillator input XCLKIN, SPI-A slave transmit enable, SCI-A receive and eCAP1; it is a group 2 pin and may glitch during power-up when the on-chip VREG is used.
26	GPIO17/SPISOMIA/TZ3	bidirectional	General-purpose I/O 17 with SPI-A slave output/master input (SPISOMIA) and trip-zone input TZ3; it is a group 2 pin.
27	GPIO16/SPISIMOA/TZ2	bidirectional	General-purpose I/O 16 with SPI-A slave input/master output (SPISIMOA) and trip-zone input TZ2; it is a group 2 pin.
28	GPIO1/EPWM1B/COMP1OUT	bidirectional	General-purpose I/O 1 with ePWM1B output and direct comparator 1 output COMP1OUT.
29	GPIO0/EPWM1A	bidirectional	General-purpose I/O 0 with ePWM1A output and HRPWM channel; PWM pins have their pull-ups disabled at reset.
30	TEST	bidirectional	Reserved for TI; it must be left unconnected.
31	GPIO32/SDAA/EPWMSYNCI/ADCSOCAO	bidirectional	General-purpose I/O 32 with I2C-A data open-drain (SDAA), ePWM external sync input (EPWMSYNCI) and ADC start-of-conversion A output (ADCSOCAO).
32	VDD	power_in	CPU and logic core supply; with the internal VREG in use, place a 1.2 µF (minimum) capacitor on each VDD pin, or supply 1.71 V to 1.995 V externally when VREG is disabled.
33	VSS	power_in	Digital ground pin.
34	VREGENZ	input	Internal voltage regulator enable with internal pull-down: tie to VSS to enable the internal 1.8 V VREG, or tie to VDDIO to disable it and supply 1.8 V externally on VDD.
35	VDDIO	power_in	Digital I/O and Flash supply (2.97 V to 3.63 V, 3.3 V nominal) that also supplies the VREG when enabled; place a decoupling capacitor on this pin.
36	GPIO33/SCLA/EPWMSYNCO/ADCSOCBO	bidirectional	General-purpose I/O 33 with I2C-A clock open-drain (SCLA), ePWM external sync output (EPWMSYNCO) and ADC start-of-conversion B output (ADCSOCBO).
37	GPIO2/EPWM2A	bidirectional	General-purpose I/O 2 with ePWM2A output and HRPWM channel.
38	GPIO3/EPWM2B/COMP2OUT	bidirectional	General-purpose I/O 3 with ePWM2B output and direct comparator 2 output COMP2OUT (48-pin device only).
39	GPIO4/EPWM3A	bidirectional	General-purpose I/O 4 with ePWM3A output and HRPWM channel.
40	GPIO5/EPWM3B/ECAP1	bidirectional	General-purpose I/O 5 with ePWM3B output and enhanced capture I/O 1 (ECAP1).
41	GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO	bidirectional	General-purpose I/O 6 with ePWM4A output and HRPWM channel, plus external ePWM sync input (EPWMSYNCI) and sync output (EPWMSYNCO).
42	GPIO7/EPWM4B/SCIRXDA	bidirectional	General-purpose I/O 7 with ePWM4B output and SCI-A receive data (SCIRXDA).
43	VDD	power_in	CPU and logic core supply; with the internal VREG in use, place a 1.2 µF (minimum) capacitor on each VDD pin.
44	VSS	power_in	Digital ground pin.
45	X1	input	1.8 V on-chip crystal oscillator input that must never receive 3.3 V signals; connect a crystal or resonator between X1 and X2, or tie to GND if unused.
46	X2	output	On-chip crystal oscillator output that must be connected to a crystal or resonator with X1, or left unconnected if unused.
47	GPIO12/TZ1/SCITXDA	bidirectional	General-purpose I/O 12 with trip-zone input TZ1 and SCI-A transmit (SCITXDA).
48	GPIO28/SCIRXDA/SDAA/TZ2	bidirectional	General-purpose I/O 28 with SCI receive data (SCIRXDA), I2C-A data open-drain (SDAA) and trip-zone input TZ2; it is a group 2 pin.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	LQFP-48(7x7)
Category	Embedded Processors & Controllers
Pins	48

CAD (KiCad official)

Symbol: TMS320F28020PTT
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: tms320f28020ptt-etched.step / tms320f28020ptt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f28020ptt.step / tms320f28020ptt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (147 pp, sha256 b90c388f4142c4b5, retrieved 2026-10-08, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF