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TMS320F28015NMFA

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LFBGA-100. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TMS320F28015NMFA

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LFBGA-100

TMS320F28015NMFA from Texas Instruments, in a LFBGA-100. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
A1 GPIO32 bidirectional GPIO32 (I/O/Z) with alternate functions I2C data SDAA, EPWMSYNCI and ADCSOCAO.
A2 GPIO26 bidirectional GPIO26 (I/O/Z) with alternate functions ECAP3, EQEP2I and SPICLKB.
A3 TEST1 unconnected Test pin reserved for TI; must be left unconnected.
A4 VSS power_in Digital ground pin.
A5 VSS power_in Digital ground pin.
A6 TRST input JTAG test reset with internal pulldown; active high, must be held low during normal operation, external pulldown required (about 2.2 kΩ).
A7 VDDIO power_in Digital I/O power pin (3.3 V).
A8 EMU0 bidirectional Emulator pin 0 (I/O/Z, 8 mA drive, pullup); external pullup of 2.2 kΩ to 4.7 kΩ recommended.
A9 VSS power_in Digital ground pin.
A10 TCK input JTAG test clock with internal pullup.
B1 VSS power_in Digital ground pin.
B2 GPIO12 bidirectional GPIO12 (I/O/Z) with alternate functions TZ1 trip zone input 1, CANTXB and SPISIMOB.
B3 TEST2 unconnected Test pin reserved for TI; must be left unconnected.
B4 GPIO13 bidirectional GPIO13 (I/O/Z) with alternate functions TZ2 trip zone input 2, CANRXB and SPISOMIB.
B5 XCLKIN input External oscillator input for a 3.3-V oscillator (tie X1 to GND); tie to GND when a crystal/resonator or 1.8-V oscillator is used.
B6 VDD power_in CPU and logic digital power pin (1.8 V).
B7 EMU1 bidirectional Emulator pin 1 (I/O/Z, 8 mA drive, pullup); external pullup of 2.2 kΩ to 4.7 kΩ recommended.
B8 XRS bidirectional Device reset input and watchdog reset output; open-drain with internal pullup, driven low 512 OSCCLK cycles on watchdog reset.
B9 TDO output JTAG scan out, test data output (O/Z, 8 mA drive), shifted on falling edge of TCK.
B10 TMS input JTAG test-mode select with internal pullup, clocked into TAP controller on rising edge of TCK.
C1 GPIO33 bidirectional GPIO33 (I/O/Z) with alternate functions I2C clock SCLA, EPWMSYNCO and ADCSOCBO.
C2 VDDIO power_in Digital I/O power pin (3.3 V).
C3 GPIO29 bidirectional GPIO29 (I/O/Z, 8 mA output buffer) with alternate functions SCITXDA and TZ6.
C4 VDD3VFL power_in 3.3-V Flash core power pin; must be connected to 3.3 V at all times.
C5 GPIO25 bidirectional GPIO25 (I/O/Z) with alternate functions ECAP2, EQEP2B and SPISOMIB.
C6 X2 output Internal oscillator output for crystal or resonator across X1 and X2; leave unconnected if not used.
C7 GPIO24 bidirectional GPIO24 (I/O/Z) with alternate functions ECAP1, EQEP2A and SPISIMOB.
C8 GPIO27 bidirectional GPIO27 (I/O/Z) with alternate functions ECAP4, EQEP2S and SPISTEB.
C9 TDI input JTAG test data input with internal pullup, clocked on rising edge of TCK.
C10 GPIO23 bidirectional GPIO23 (I/O/Z) with alternate functions EQEP1I, SPISTEC and SCIRXDB.
D1 GPIO31 bidirectional GPIO31 (I/O/Z, 8 mA output buffer) with CANTXA alternate function (CAN-A not applicable on F28015).
D2 GPIO30 bidirectional GPIO30 (I/O/Z, 8 mA output buffer) with CANRXA alternate function (CAN-A not applicable on F28015).
D3 GPIO14 bidirectional GPIO14 (I/O/Z) with alternate functions TZ3 trip zone input 3, SCITXDB and SPICLKB.
D4 VDD power_in CPU and logic digital power pin (1.8 V).
D5 GPIO28 bidirectional GPIO28 (I/O/Z, 8 mA output buffer) with alternate functions SCIRXDA and TZ5.
D6 VSS power_in Digital ground pin.
D7 VDD power_in CPU and logic digital power pin (1.8 V).
D8 GPIO22 bidirectional GPIO22 (I/O/Z) with alternate functions EQEP1S, SPICLKC and SCITXDB.
D9 GPIO11 bidirectional GPIO11 (I/O/Z) with alternate functions EPWM6B, SCIRXDB and ECAP4.
D10 VSS power_in Digital ground pin.
E1 GPIO15 bidirectional GPIO15 (I/O/Z) with alternate functions TZ4 trip zone input 4, SCIRXDB and SPISTEB.
E2 VDD power_in CPU and logic digital power pin (1.8 V).
E3 VSS power_in Digital ground pin.
E4 VDD1A18 power_in ADC analog power pin (1.8 V).
E5 VSS1AGND power_in ADC analog ground pin.
E6 X1 input Internal/external oscillator input referenced to 1.8-V core supply; tie to GND if a 3.3-V oscillator is used on XCLKIN.
E7 GPIO21 bidirectional GPIO21 (I/O/Z) with alternate functions EQEP1B, SPISOMIC and CANRXB.
E8 XCLKOUT output Output clock derived from SYSCLKOUT at 1x, 1/2 or 1/4 frequency (O/Z, 8 mA drive); not high-impedance during reset.
E9 VDDIO power_in Digital I/O power pin (3.3 V).
E10 GPIO10 bidirectional GPIO10 (I/O/Z) with alternate functions EPWM6A, CANRXB and ADCSOCBO.
F1 VSSA2 power_in ADC analog ground pin.
F2 VDDA2 power_in ADC analog power pin (3.3 V).
F3 ADCINA7 input ADC group A channel 7 input.
F4 ADCINA6 input ADC group A channel 6 input.
F5 ADCRESEXT passive ADC external current bias resistor; connect a 22-kΩ resistor to analog ground.
F6 GPIO20 bidirectional GPIO20 (I/O/Z) with alternate functions EQEP1A, SPISIMOC and CANTXB.
F7 VSS power_in Digital ground pin.
F8 GPIO9 bidirectional GPIO9 (I/O/Z) with alternate functions EPWM5B, SCITXDB and ECAP3.
F9 GPIO8 bidirectional GPIO8 (I/O/Z) with alternate functions EPWM5A, CANTXB and ADCSOCAO.
F10 VDD power_in CPU and logic digital power pin (1.8 V).
G1 ADCINA4 input ADC group A channel 4 input.
G2 ADCINA3 input ADC group A channel 3 input.
G3 ADCINA2 input ADC group A channel 2 input.
G4 ADCINA5 input ADC group A channel 5 input.
G5 ADCREFP output Internal reference positive output; needs low-ESR (under 1.5 Ω) 2.2 μF ceramic capacitor to analog ground.
G6 VDD power_in CPU and logic digital power pin (1.8 V).
G7 GPIO34 bidirectional General-purpose input/output 34 (I/O/Z) with no alternate peripheral functions.
G8 GPIO7 bidirectional GPIO7 (I/O/Z) with alternate functions EPWM4B, SPISTED and ECAP2.
G9 GPIO6 bidirectional GPIO6 (I/O/Z) with alternate functions EPWM4A, EPWMSYNCI and EPWMSYNCO.
G10 GPIO19 bidirectional GPIO19 (I/O/Z) with alternate functions SPISTEA and SCIRXDB.
H1 ADCINA1 input ADC group A channel 1 input.
H2 ADCINA0 input ADC group A channel 0 input.
H3 ADCINB2 input ADC group B channel 2 input.
H4 ADCINB6 input ADC group B channel 6 input.
H5 ADCREFM output Internal reference medium output; needs low-ESR (under 1.5 Ω) 2.2 μF ceramic capacitor to analog ground.
H6 VSS power_in Digital ground pin.
H7 VDDIO power_in Digital I/O power pin (3.3 V).
H8 GPIO18 bidirectional GPIO18 (I/O/Z) with alternate functions SPICLKA and SCITXDB.
H9 GPIO5 bidirectional GPIO5 (I/O/Z) with alternate functions EPWM3B, SPICLKD and ECAP1.
H10 VSS power_in Digital ground pin.
J1 ADCLO input ADC low reference; connect to analog ground.
J2 VDDAIO power_in ADC analog I/O power pin (3.3 V).
J3 ADCINB1 input ADC group B channel 1 input.
J4 ADCINB4 input ADC group B channel 4 input.
J5 ADCREFIN input External reference input to the ADC.
J6 VDD2A18 power_in ADC analog power pin (1.8 V).
J7 GPIO2 bidirectional GPIO2 (I/O/Z) with alternate function EPWM2A.
J8 GPIO3 bidirectional GPIO3 (I/O/Z) with alternate functions EPWM2B and SPISOMID.
J9 GPIO4 bidirectional GPIO4 (I/O/Z) with alternate function EPWM3A.
J10 GPIO17 bidirectional GPIO17 (I/O/Z) with alternate functions SPISOMIA, CANRXB and TZ6.
K1 VSSAIO power_in ADC analog I/O ground pin.
K2 ADCINB0 input ADC group B channel 0 input.
K3 ADCINB3 input ADC group B channel 3 input.
K4 ADCINB5 input ADC group B channel 5 input.
K5 ADCINB7 input ADC group B channel 7 input.
K6 VSS2AGND power_in ADC analog ground pin.
K7 GPIO1 bidirectional GPIO1 (I/O/Z) with alternate functions EPWM1B and SPISIMOD.
K8 GPIO0 bidirectional GPIO0 (I/O/Z) with alternate function EPWM1A.
K9 VSS power_in Digital ground pin.
K10 GPIO16 bidirectional GPIO16 (I/O/Z) with alternate functions SPISIMOA, CANTXB and TZ5.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LFBGA-100
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: TMS320F28015NMFA
  • Footprint: Package_BGA:LFBGA-100_10x10mm_Layout10x10_P0.8mm
  • 3D model: LFBGA-100 (KiCad packages3D, STEP)
  • 3D model files: tms320f28015nmfa-etched.step / tms320f28015nmfa-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f28015nmfa.step / tms320f28015nmfa.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (157 pp, sha256 a13113c4c002c567, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF