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TMS320C54CSTPGE

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-144(20x20). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TMS320C54CSTPGE

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-144(20x20)

TMS320C54CSTPGE from Texas Instruments, in a LQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VSS power_in Ground for both the I/O pins and the core CPU.
2 A22 tri_state Address bus MSB (A22); upper address pins A22-A16 address external program space only and go high-impedance in hold mode or when OFF is low.
3 VSS power_in Ground for both the I/O pins and the core CPU.
4 DVDD power_in 3.3-V supply for the I/O pins.
5 A10 tri_state Parallel address bus bit A10; high-impedance in hold mode or when OFF is low; HPI address input when HPI16 is high.
6 HD7 bidirectional HPI data bus bit 7, also usable as general-purpose I/O.
7 A11 tri_state Parallel address bus bit A11; high-impedance in hold mode or when OFF is low; HPI address input when HPI16 is high.
8 A12 tri_state Parallel address bus bit A12; high-impedance in hold mode or when OFF is low; HPI address input when HPI16 is high.
9 A13 tri_state Parallel address bus bit A13; high-impedance in hold mode or when OFF is low; HPI address input when HPI16 is high.
10 A14 tri_state Parallel address bus bit A14; high-impedance in hold mode or when OFF is low; HPI address input when HPI16 is high.
11 A15 tri_state Parallel address bus bit A15 (MSB of lower address); high-impedance in hold mode or when OFF is low; HPI address MSB input when HPI16 is high.
12 CVDD power_in 1.5-V supply for the core CPU.
13 HAS input Host-port interface address strobe input.
14 VSS power_in Ground for both the I/O pins and the core CPU.
15 VSS power_in Ground for both the I/O pins and the core CPU.
16 CVDD power_in 1.5-V supply for the core CPU.
17 HCS input Host-port interface chip select input.
18 HR/W input Host-port interface read/write input.
19 READY input External device ready input used to insert wait states.
20 PS tri_state Program space select strobe output.
21 DS tri_state Data space select strobe output.
22 IS tri_state I/O space select strobe output.
23 R/W tri_state Read/write signal output for external accesses.
24 MSTRB tri_state Memory strobe output for external memory accesses.
25 IOSTRB tri_state I/O strobe output for external I/O accesses.
26 MSC output Microstate complete output.
27 XF output External flag output; general-purpose output pin.
28 HOLDA output Hold acknowledge output.
29 IAQ tri_state Instruction acquisition output.
30 HOLD input Hold request input.
31 BIO input Branch control input; general-purpose input pin.
32 MP/MC input Microprocessor/microcomputer mode select input.
33 DVDD power_in 3.3-V supply for the I/O pins.
34 VSS power_in Ground for both the I/O pins and the core CPU.
35 DAAEN input DAA enable pin.
36 BFSRX2 bidirectional McBSP2 frame sync pin used for the DAA interface; usable as general-purpose I/O.
37 VSS power_in Ground for both the I/O pins and the core CPU.
38 TX output UART transmit data output (SOUT).
39 HCNTL0 input Host-port interface control input 0.
40 VSS power_in Ground for both the I/O pins and the core CPU.
41 BCLKR0 bidirectional McBSP0 receive clock; usable as general-purpose I/O.
42 BCLKR1 bidirectional McBSP1 receive clock; usable as general-purpose I/O.
43 BFSR0 bidirectional McBSP0 receive frame sync; usable as general-purpose I/O.
44 BFSR1 bidirectional McBSP1 receive frame sync; usable as general-purpose I/O.
45 BDR0 input McBSP0 serial data receive; usable as general-purpose input.
46 HCNTL1 input Host-port interface control input 1.
47 BDR1 input McBSP1 serial data receive; usable as general-purpose input.
48 BCLKX0 bidirectional McBSP0 transmit clock; usable as general-purpose I/O.
49 BCLKX1 bidirectional McBSP1 transmit clock; usable as general-purpose I/O.
50 VSS power_in Ground for both the I/O pins and the core CPU.
51 HINT/TOUT1 output Host-port interrupt output / Timer 1 output.
52 CVDD power_in 1.5-V supply for the core CPU.
53 BFSX0 bidirectional McBSP0 transmit frame sync; usable as general-purpose I/O.
54 BFSX1 bidirectional McBSP1 transmit frame sync; usable as general-purpose I/O.
55 HRDY output Host-port interface ready output.
56 DVDD power_in 3.3-V supply for the I/O pins.
57 VSS power_in Ground for both the I/O pins and the core CPU.
58 HD0 bidirectional HPI data bus bit 0, also general-purpose I/O (UART DTR input by default in CST software).
59 BDX0 output McBSP0 serial data transmit; usable as general-purpose output.
60 BDX1 output McBSP1 serial data transmit; usable as general-purpose output.
61 IACK output Interrupt acknowledge output.
62 HBIL input Host-port interface byte identification input.
63 NMI input Nonmaskable interrupt input.
64 INT0 input External user interrupt 0 input.
65 INT1 input External user interrupt 1 input.
66 INT2 input External user interrupt 2 input.
67 INT3 input External user interrupt 3 input, ORed with Timer 1 interrupt; tie high if Timer1 interrupt is used.
68 CVDD power_in 1.5-V supply for the core CPU.
69 HD1 bidirectional HPI data bus bit 1, also general-purpose I/O (UART RTS input by default in CST software).
70 VSS power_in Ground for both the I/O pins and the core CPU.
71 RX input UART receive data input (SIN).
72 VSS power_in Ground for both the I/O pins and the core CPU.
73 C1A bidirectional Capacitively coupled isolation link to Si3016 C1B; driver rated for max 10 pF load.
74 C1A5V power_in 5-V supply input used only by the C1A driver; needs a 0.22 uF bypass close to the pin.
75 DVDD power_in 3.3-V supply for the I/O pins.
76 VSS power_in Ground for both the I/O pins and the core CPU.
77 CLKMD1 input Clock mode select 1, sampled while RS is low to set the reset clock mode.
78 CLKMD2 input Clock mode select 2, sampled while RS is low to set the reset clock mode.
79 CLKMD3 input Clock mode select 3, sampled while RS is low to set the reset clock mode.
80 HPI16 input HPI16 mode select; when high, A0-A15 address internal memory via the HPI.
81 HD2 bidirectional HPI data bus bit 2, also general-purpose I/O (UART CTS output by default in CST software).
82 TOUT output Timer output.
83 EMU0 bidirectional Emulator interrupt 0 pin.
84 EMU1/OFF bidirectional Emulator interrupt 1 / OFF; when low, address and data buses go high-impedance.
85 TDO output JTAG test data output.
86 TDI input JTAG test data input with internal pullup.
87 TRST input JTAG test reset with internal pulldown; a 470-ohm external pulldown is required.
88 TCK input JTAG test clock input with internal pullup.
89 TMS input JTAG test mode select input with internal pullup.
90 VSS power_in Ground for both the I/O pins and the core CPU.
91 CVDD power_in 1.5-V supply for the core CPU.
92 HPIENA input HPI enable input with internal pulldown.
93 VSS power_in Ground for both the I/O pins and the core CPU.
94 CLKOUT output Clock output; can be disabled with CLKOUT off control.
95 HD3 bidirectional HPI data bus bit 3, also general-purpose I/O (UART DSR output by default in CST software).
96 X1 output Crystal oscillator output; left unconnected when an external clock drives X2/CLKIN.
97 X2/CLKIN input Crystal connection / external reference clock input.
98 RS input Device reset input.
99 D0 bidirectional Data bus bit 0 (LSB); high-impedance when not outputting or when RS or HOLD asserted; has bus holder.
100 D1 bidirectional Data bus bit 1; high-impedance when not outputting or when RS or HOLD asserted; has bus holder.
101 D2 bidirectional Data bus bit 2; high-impedance when not outputting or when RS or HOLD asserted; has bus holder.
102 D3 bidirectional Data bus bit 3; high-impedance when not outputting or when RS or HOLD asserted; has bus holder.
103 D4 bidirectional Data bus bit 4; high-impedance when not outputting or when RS or HOLD asserted; has bus holder.
104 D5 bidirectional Data bus bit 5; high-impedance when not outputting or when RS or HOLD asserted; has bus holder.
105 A16 tri_state Address bus bit A16; upper address pins address external program space only; high-impedance in hold mode or when OFF is low.
106 VSS power_in Ground for both the I/O pins and the core CPU.
107 A17 tri_state Address bus bit A17; upper address pins address external program space only; high-impedance in hold mode or when OFF is low.
108 A18 tri_state Address bus bit A18; upper address pins address external program space only; high-impedance in hold mode or when OFF is low.
109 A19 tri_state Address bus bit A19; upper address pins address external program space only; high-impedance in hold mode or when OFF is low.
110 A20 tri_state Address bus bit A20; upper address pins address external program space only; high-impedance in hold mode or when OFF is low.
111 VSS power_in Ground for both the I/O pins and the core CPU.
112 DVDD power_in 3.3-V supply for the I/O pins.
113 D6 bidirectional Data bus bit 6; high-impedance when not outputting or when RS or HOLD asserted; has bus holder.
114 D7 bidirectional Data bus bit 7; high-impedance when not outputting or when RS or HOLD asserted; has bus holder.
115 D8 bidirectional Data bus bit 8; high-impedance when not outputting or when RS or HOLD asserted; has bus holder.
116 D9 bidirectional Data bus bit 9; high-impedance when not outputting or when RS or HOLD asserted; has bus holder.
117 D10 bidirectional Data bus bit 10; high-impedance when not outputting or when RS or HOLD asserted; has bus holder.
118 D11 bidirectional Data bus bit 11; high-impedance when not outputting or when RS or HOLD asserted; has bus holder.
119 D12 bidirectional Data bus bit 12; high-impedance when not outputting or when RS or HOLD asserted; has bus holder.
120 HD4 bidirectional HPI data bus bit 4, also general-purpose I/O (UART DCD output by default in CST software).
121 D13 bidirectional Data bus bit 13; high-impedance when not outputting or when RS or HOLD asserted; has bus holder.
122 D14 bidirectional Data bus bit 14; high-impedance when not outputting or when RS or HOLD asserted; has bus holder.
123 D15 bidirectional Data bus bit 15 (MSB); high-impedance when not outputting or when RS or HOLD asserted; has bus holder.
124 HD5 bidirectional HPI data bus bit 5, also general-purpose I/O (UART RI output by default in CST software).
125 CVDD power_in 1.5-V supply for the core CPU.
126 VSS power_in Ground for both the I/O pins and the core CPU.
127 HDS1 input Host-port interface data strobe 1 input.
128 VSS power_in Ground for both the I/O pins and the core CPU.
129 HDS2 input Host-port interface data strobe 2 input.
130 DVDD power_in 3.3-V supply for the I/O pins.
131 A0 tri_state Address bus LSB (A0); high-impedance in hold mode or when OFF is low; HPI address input when HPI16 is high.
132 A1 tri_state Parallel address bus bit A1; high-impedance in hold mode or when OFF is low; HPI address input when HPI16 is high.
133 A2 tri_state Parallel address bus bit A2; high-impedance in hold mode or when OFF is low; HPI address input when HPI16 is high.
134 A3 tri_state Parallel address bus bit A3; high-impedance in hold mode or when OFF is low; HPI address input when HPI16 is high.
135 HD6 bidirectional HPI data bus bit 6, also usable as general-purpose I/O.
136 A4 tri_state Parallel address bus bit A4; high-impedance in hold mode or when OFF is low; HPI address input when HPI16 is high.
137 A5 tri_state Parallel address bus bit A5; high-impedance in hold mode or when OFF is low; HPI address input when HPI16 is high.
138 A6 tri_state Parallel address bus bit A6; high-impedance in hold mode or when OFF is low; HPI address input when HPI16 is high.
139 A7 tri_state Parallel address bus bit A7; high-impedance in hold mode or when OFF is low; HPI address input when HPI16 is high.
140 A8 tri_state Parallel address bus bit A8; high-impedance in hold mode or when OFF is low; HPI address input when HPI16 is high.
141 A9 tri_state Parallel address bus bit A9; high-impedance in hold mode or when OFF is low; HPI address input when HPI16 is high.
142 CVDD power_in 1.5-V supply for the core CPU.
143 A21 tri_state Address bus bit A21; upper address pins address external program space only; high-impedance in hold mode or when OFF is low.
144 VSS power_in Ground for both the I/O pins and the core CPU.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-144(20x20)
Category Embedded Processors & Controllers
Pins 144

CAD (KiCad official)

  • Symbol: TMS320C54CSTPGE
  • Footprint: Package_QFP:LQFP-144_20x20mm_P0.5mm
  • 3D model: LQFP-144(20x20) (KiCad packages3D, STEP)
  • 3D model files: tms320c54cstpge-etched.step / tms320c54cstpge-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320c54cstpge.step / tms320c54cstpge.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (177 pp, sha256 64b3abcace713a90, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF