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TMP4080NF

Tritech MOS · MOSFETs · DFN-8(5x6)

TMP4080NF from Tritech MOS, in a DFN-8(5x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S passive Source of the P-channel MOSFET; pin 1 is at the marked corner, and VDS is rated -40 V.
2 S passive Source of the P-channel MOSFET, shorted externally with the other source pins.
3 S passive Source of the P-channel MOSFET, shorted externally with the other source pins.
4 G input Gate of the P-channel MOSFET; VGS is rated ±20 V and the threshold VGS(th) is -1 to -2.5 V.
5 D passive Drain of the MOSFET; continuous drain current is -80 A at TC=25°C.
6 D passive Drain of the MOSFET, shorted externally with the other drain pins.
7 D passive Drain of the MOSFET, shorted externally with the other drain pins.
8 D passive Drain of the MOSFET, shorted externally with the other drain pins.
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Tritech MOS
Package DFN-8(5x6)
Category Transistors/Thyristors
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Voltage VDS -40 V 1
Gate-Source Voltage VGS -20 20 V 1
Continuous Drain Current ID -80 A VGS @ -10V, TC=25℃ 1
Continuous Drain Current ID -56 A VGS @ -10V, TC=100℃ 1
Pulsed Drain Current IDM -320 A 1
Single Pulse Avalanche Energy EAS 576 mJ 1
Avalanche Current IAS -56 A 1
Total Power Dissipation PD 58 W TC=25℃ 1
Storage Temperature Range TSTG -55 175 ℃ 1
Operating Junction Temperature Range TJ -55 175 ℃ 1
Thermal Resistance Junction-ambient RθJA 20 ℃/W t≦10S 1
Thermal Resistance Junction-ambient RθJA 50 ℃/W Steady State 1
Thermal Resistance Junction-case RθJC 1.6 ℃/W 1
Drain-Source Breakdown Voltage BVDSS -40 V VGS=0V ID=-250μA 2
Zero Gate Voltage Drain Current IDSS -1 μA VDS=-40V, VGS=0V 2
Gate-Body Leakage Current IGSS -100 100 nA VGS=±20V, VDS=0V 2
Gate Threshold Voltage VGS(th) -1 -1.7 -2.5 V VDS=VGS, ID=-250μA 2
Drain-Source On-State Resistance RDS(ON) 4.3 5.3 mΩ VGS=-10V, ID=-20A 2
Drain-Source On-State Resistance RDS(ON) 5.9 7.6 mΩ VGS=-4.5V, ID=-20A 2

CAD (KiCad official)

  • Symbol: TMP4080NF
  • Footprint: Package_DFN_QFN:DFN-S-8-1EP_6x5mm_P1.27mm
  • 3D model: DFN-8(5x6) (KiCad packages3D, STEP)
  • 3D model files: tmp4080nf-etched.step / tmp4080nf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tmp4080nf.step / tmp4080nf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Tritech MOS datasheet (6 pp, sha256 ac4697ab958661c0, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF