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TMDS341APFCR

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Texas Instruments Interface - Specialized, TQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232tmds341apfcrfactory-2.0.0extractor-text
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TMDS341APFCR

Texas Instruments · Interface - Specialized · TQFP-80(12x12)

TMDS341APFCR from Texas Instruments, in a TQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No internal connection; leave this pin unconnected.
2 SDA1 bidirectional Port 1 DDC bus data line, 5-V tolerant with a maximum input voltage of 5.5 V.
3 SCL1 bidirectional Port 1 DDC bus clock line, 5-V tolerant with a maximum input voltage of 5.5 V.
4 GND power_in Ground.
5 B11 input Port 1 TMDS negative input, receiver with integrated 50-Ω termination to VCC and 8-dB equalization.
6 A11 input Port 1 TMDS positive input, receiver with integrated 50-Ω termination to VCC and 8-dB equalization.
7 VCC power_in 3.3-V supply pin; recommended supply range is 3 V to 3.6 V with a 0.01-µF capacitor to ground.
8 B12 input Port 1 TMDS negative input, receiver with integrated 50-Ω termination to VCC and 8-dB equalization.
9 A12 input Port 1 TMDS positive input, receiver with integrated 50-Ω termination to VCC and 8-dB equalization.
10 GND power_in Ground.
11 B13 input Port 1 TMDS negative input, receiver with integrated 50-Ω termination to VCC and 8-dB equalization.
12 A13 input Port 1 TMDS positive input, receiver with integrated 50-Ω termination to VCC and 8-dB equalization.
13 VCC power_in 3.3-V supply pin; recommended supply range is 3 V to 3.6 V with a 0.01-µF capacitor to ground.
14 B14 input Port 1 TMDS negative input, receiver with integrated 50-Ω termination to VCC and 8-dB equalization.
15 A14 input Port 1 TMDS positive input, receiver with integrated 50-Ω termination to VCC and 8-dB equalization.
16 GND power_in Ground.
17 VCC power_in 3.3-V supply pin; recommended supply range is 3 V to 3.6 V with a 0.01-µF capacitor to ground.
18 VSADJ input TMDS swing control; a 1% precision resistor of about 4.64 kΩ (range 4.6 to 4.68 kΩ) to ground sets the differential output voltage to TMDS levels.
19 PRE input Output de-emphasis select: high selects 3 dB, low selects 0 dB; low is recommended for a stand-alone switch box.
20 NC unconnected No internal connection; leave this pin unconnected.
21 S1 input Source selector for Port 1; LVTTL input with logic high level of at least 2 V and low level of at most 0.8 V, selecting the active source per Table 1.
22 S2 input Source selector for Port 2; LVTTL input with logic high level of at least 2 V and low level of at most 0.8 V, selecting the active source per Table 1.
23 S3 input Source selector for Port 3; LVTTL input with logic high level of at least 2 V and low level of at most 0.8 V, selecting the active source per Table 1.
24 GND power_in Ground.
25 Y4 output TMDS positive output for the selected source, with 45-55 Ω termination resistance and AVCC of 3 V to 3.6 V.
26 Z4 output TMDS negative output for the selected source, with 45-55 Ω termination resistance and AVCC of 3 V to 3.6 V.
27 VCC power_in 3.3-V supply pin; recommended supply range is 3 V to 3.6 V with a 0.01-µF capacitor to ground.
28 Y3 output TMDS positive output for the selected source, with 45-55 Ω termination resistance and AVCC of 3 V to 3.6 V.
29 Z3 output TMDS negative output for the selected source, with 45-55 Ω termination resistance and AVCC of 3 V to 3.6 V.
30 GND power_in Ground.
31 Y2 output TMDS positive output for the selected source, with 45-55 Ω termination resistance and AVCC of 3 V to 3.6 V.
32 Z2 output TMDS negative output for the selected source, with 45-55 Ω termination resistance and AVCC of 3 V to 3.6 V.
33 VCC power_in 3.3-V supply pin; recommended supply range is 3 V to 3.6 V with a 0.01-µF capacitor to ground.
34 Y1 output TMDS positive output for the selected source, with 45-55 Ω termination resistance and AVCC of 3 V to 3.6 V.
35 Z1 output TMDS negative output for the selected source, with 45-55 Ω termination resistance and AVCC of 3 V to 3.6 V.
36 GND power_in Ground.
37 GND power_in Ground.
38 SCL_SINK bidirectional Sink-side DDC bus clock line, 5-V tolerant with a maximum input voltage of 5.5 V.
39 SDA_SINK bidirectional Sink-side DDC bus data line, 5-V tolerant with a maximum input voltage of 5.5 V.
40 HPD_SINK input Sink-side hot plug detect input, 5-V tolerant; high (2 V to 5.3 V) means 5-V power is present and EDID is ready, low (at most 0.8 V) means not.
41 NC unconnected No internal connection; leave this pin unconnected.
42 OE input Output enable, active low; when high with a standard TMDS termination the TMDS outputs are high impedance.
43 VCC power_in 3.3-V supply pin; recommended supply range is 3 V to 3.6 V with a 0.01-µF capacitor to ground.
44 HPD3 output Port 3 hot plug detect output, which passes HPD_SINK when Port 3 is selected and is held low otherwise; about 35 Ω typical output resistance, with a 1-kΩ 10% series resistor recommended.
45 SDA3 bidirectional Port 3 DDC bus data line, 5-V tolerant with a maximum input voltage of 5.5 V.
46 SCL3 bidirectional Port 3 DDC bus clock line, 5-V tolerant with a maximum input voltage of 5.5 V.
47 GND power_in Ground.
48 B31 input Port 3 TMDS negative input, receiver with integrated 50-Ω termination to VCC and 8-dB equalization.
49 A31 input Port 3 TMDS positive input, receiver with integrated 50-Ω termination to VCC and 8-dB equalization.
50 VCC power_in 3.3-V supply pin; recommended supply range is 3 V to 3.6 V with a 0.01-µF capacitor to ground.
51 B32 input Port 3 TMDS negative input, receiver with integrated 50-Ω termination to VCC and 8-dB equalization.
52 A32 input Port 3 TMDS positive input, receiver with integrated 50-Ω termination to VCC and 8-dB equalization.
53 GND power_in Ground.
54 B33 input Port 3 TMDS negative input, receiver with integrated 50-Ω termination to VCC and 8-dB equalization.
55 A33 input Port 3 TMDS positive input, receiver with integrated 50-Ω termination to VCC and 8-dB equalization.
56 VCC power_in 3.3-V supply pin; recommended supply range is 3 V to 3.6 V with a 0.01-µF capacitor to ground.
57 B34 input Port 3 TMDS negative input, receiver with integrated 50-Ω termination to VCC and 8-dB equalization.
58 A34 input Port 3 TMDS positive input, receiver with integrated 50-Ω termination to VCC and 8-dB equalization.
59 GND power_in Ground.
60 NC unconnected No internal connection; leave this pin unconnected.
61 VCC power_in 3.3-V supply pin; recommended supply range is 3 V to 3.6 V with a 0.01-µF capacitor to ground.
62 HPD2 output Port 2 hot plug detect output, which passes HPD_SINK when Port 2 is selected and is held low otherwise; about 35 Ω typical output resistance, with a 1-kΩ 10% series resistor recommended.
63 SDA2 bidirectional Port 2 DDC bus data line, 5-V tolerant with a maximum input voltage of 5.5 V.
64 SCL2 bidirectional Port 2 DDC bus clock line, 5-V tolerant with a maximum input voltage of 5.5 V.
65 GND power_in Ground.
66 GND power_in Ground.
67 B21 input Port 2 TMDS negative input, receiver with integrated 50-Ω termination to VCC and 8-dB equalization.
68 A21 input Port 2 TMDS positive input, receiver with integrated 50-Ω termination to VCC and 8-dB equalization.
69 VCC power_in 3.3-V supply pin; recommended supply range is 3 V to 3.6 V with a 0.01-µF capacitor to ground.
70 B22 input Port 2 TMDS negative input, receiver with integrated 50-Ω termination to VCC and 8-dB equalization.
71 A22 input Port 2 TMDS positive input, receiver with integrated 50-Ω termination to VCC and 8-dB equalization.
72 GND power_in Ground.
73 B23 input Port 2 TMDS negative input, receiver with integrated 50-Ω termination to VCC and 8-dB equalization.
74 A23 input Port 2 TMDS positive input, receiver with integrated 50-Ω termination to VCC and 8-dB equalization.
75 VCC power_in 3.3-V supply pin; recommended supply range is 3 V to 3.6 V with a 0.01-µF capacitor to ground.
76 B24 input Port 2 TMDS negative input, receiver with integrated 50-Ω termination to VCC and 8-dB equalization.
77 A24 input Port 2 TMDS positive input, receiver with integrated 50-Ω termination to VCC and 8-dB equalization.
78 GND power_in Ground.
79 VCC power_in 3.3-V supply pin; recommended supply range is 3 V to 3.6 V with a 0.01-µF capacitor to ground.
80 HPD1 output Port 1 hot plug detect output, which passes HPD_SINK when Port 1 is selected and is held low otherwise; about 35 Ω typical output resistance, with a 1-kΩ 10% series resistor recommended.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-80(12x12)
Category Communication Interface Chip/UART/485/232
Pins 80

CAD (KiCad official)

  • Symbol: TMDS341APFCR
  • Footprint: Package_QFP:TQFP-80_12x12mm_P0.5mm
  • 3D model: TQFP-80(12x12) (KiCad packages3D, STEP)
  • 3D model files: tmds341apfcr-etched.step / tmds341apfcr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tmds341apfcr.step / tmds341apfcr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (32 pp, sha256 d4b5ddfc7a56b285, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF