# TMDS181RGZR

**Texas Instruments** · Interface - Specialized · QFN-48-EP(7x7)

TMDS181RGZR from Texas Instruments, in a QFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SWAP/POL | input | 3-level input lane SWAP and polarity control pin with H selecting polarity swap in retimer mode, L selecting lanes swap, and NC selecting normal operation. |
| 2 | IN_D2p | input | Channel 2 differential input pair for main link TMDS data transmission. |
| 3 | IN_D2n | input | Channel 2 differential input pair for main link TMDS data transmission. |
| 4 | HPD_SRC | output | Hot plug detect output to source side. |
| 5 | IN_D1p | input | Channel 1 differential input pair for main link TMDS data transmission. |
| 6 | IN_D1n | input | Channel 1 differential input pair for main link TMDS data transmission. |
| 7 | GND | power_in | Ground. |
| 8 | IN_D0p | input | Channel 0 differential input pair for main link TMDS data transmission. |
| 9 | IN_D0n | input | Channel 0 differential input pair for main link TMDS data transmission. |
| 10 | I2C_EN/PIN | input | I2C Enable/Pin strap mode select input where high level puts device into I2C control mode and low level puts device into pin strap mode. |
| 11 | IN_CLKp | input | Clock differential input pair for main link TMDS clock transmission. |
| 12 | IN_CLKn | input | Clock differential input pair for main link TMDS clock transmission. |
| 13 | VCC | power_in | 3.3 V power supply. |
| 14 | VDD | power_in | 1.2 V power supply. |
| 15 | SCL_CTL | input | I2C clock signal input for I2C control interface. |
| 16 | SDA_CTL | bidirectional | I2C data signal bidirectional pin for I2C control interface. |
| 17 | SIG_EN | input | Signal detector circuit enable input with internal weak pull-down where low disables and high enables the signal detect circuit. |
| 18 | NC | unconnected | No connect. |
| 19 | GND | power_in | Ground. |
| 20 | PRE_SEL | input | 3-level de-emphasis control input when I2C_EN/PIN is low where L selects -2 dB and NC selects 0 dB. |
| 21 | EQ_SEL/A0 | input | 3-level input receive equalization control when I2C_EN/PIN is low or I2C address bit 0 when high. |
| 22 | VSADJ | input | TMDS-compliant voltage swing control input using nominal resistor value of 4.5 kΩ to 7.06 kΩ to GND. |
| 23 | VDD | power_in | 1.2 V power supply. |
| 24 | VDD | power_in | 1.2 V power supply. |
| 25 | OUT_CLKn | output | TMDS data clock differential output pair with fail-safe capability. |
| 26 | OUT_CLKp | output | TMDS data clock differential output pair with fail-safe capability. |
| 27 | A1 | input | I2C address bit 2 input with internal weak pull-down for I2C programming. |
| 28 | OUT_D0n | output | TMDS data 0 differential output pair with fail-safe capability. |
| 29 | OUT_D0p | output | TMDS data 0 differential output pair with fail-safe capability. |
| 30 | GND | power_in | Ground. |
| 31 | OUT_D1n | output | TMDS data 1 differential output pair with fail-safe capability. |
| 32 | OUT_D1p | output | TMDS data 1 differential output pair with fail-safe capability. |
| 33 | HPD_SNK | input | Hot plug detect input from sink side. |
| 34 | OUT_D2n | output | TMDS data 2 differential output pair with fail-safe capability. |
| 35 | OUT_D2p | output | TMDS data 2 differential output pair with fail-safe capability. |
| 36 | TX_TERM_CTL | input | 3-level transmit termination control input where H disables termination, L enables 75-150 Ω termination, and NC selects automatic termination based on data rate. |
| 37 | VDD | power_in | 1.2 V power supply. |
| 38 | SCL_SNK | bidirectional | Sink side TMDS port bidirectional DDC clock line. |
| 39 | SDA_SNK | bidirectional | Sink side TMDS port bidirectional DDC data line. |
| 40 | NC | unconnected | No connect. |
| 41 | GND | power_in | Ground. |
| 42 | OE | input | Operation enable/reset input where low selects power-down mode and high selects normal operation with internal weak pull-up. |
| 43 | VCC | power_in | 3.3 V power supply. |
| 44 | ARC_OUT | bidirectional | Audio return channel output signal. |
| 45 | SPDIF_IN | bidirectional | SPDIF signal input. |
| 46 | SCL_SRC | bidirectional | Source side TMDS port bidirectional DDC clock line. |
| 47 | SDA_SRC | bidirectional | Source side TMDS port bidirectional DDC data line. |
| 48 | VDD | power_in | 1.2 V power supply. |
| 49 | GND | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | QFN-48-EP(7x7) |
| Category | Interface |
| Pins | 49 |

## CAD (KiCad official)

- Symbol: `TMDS181RGZR`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`
- 3D model: QFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files: `tmds181rgzr-etched.step` / `tmds181rgzr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tmds181rgzr.step` / `tmds181rgzr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tmds181) (59 pp, sha256 `80f8eef3073a8094`, retrieved 2026-10-06, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tmds181rgzr-datasheet.pdf)