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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

TMDS181IRGZT

Texas Instruments · Interface - Specialized · VQFN-48-EP(7x7)

TMDS181IRGZT from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SWAP/POL	input	Three-level input lane swap and polarity control: H gives receive lane polarity swap (retimer mode only), L gives receive lane swap (redriver and retimer modes), and no connect gives normal operation.
2	IN_D2p	input	TMDS channel 2 differential input, positive side of the main link.
3	IN_D2n	input	TMDS channel 2 differential input, negative side of the main link.
4	HPD_SRC	output	Hot plug detect output to the source side.
5	IN_D1p	input	TMDS channel 1 differential input, positive side of the main link.
6	IN_D1n	input	TMDS channel 1 differential input, negative side of the main link.
7	GND	power_in	Ground.
8	IN_D0p	input	TMDS channel 0 differential input, positive side of the main link.
9	IN_D0n	input	TMDS channel 0 differential input, negative side of the main link.
10	I2C_EN/PIN	input	High puts the device into I2C control mode; low puts the device into pin strap mode.
11	IN_CLKp	input	Clock differential input, positive side of the main link.
12	IN_CLKn	input	Clock differential input, negative side of the main link.
13	VCC	power_in	3.3 V power supply.
14	VDD	power_in	1.2 V power supply.
15	SCL_CTL	input	I2C clock signal; when I2C_EN is low, pin strapping takes priority and these functions cannot be changed by I2C.
16	SDA_CTL	bidirectional	I2C data signal; when I2C_EN is low, pin strapping takes priority and these functions cannot be changed by I2C.
17	SIG_EN	input	Signal detector circuit enable: high enables the signal detect circuit, low disables it; internal weak pull-down.
18	NC	unconnected	No connect.
19	GND	power_in	Ground.
20	PRE_SEL	input	Three-level de-emphasis control when I2C_EN/PIN is low: L = -2 dB, no connect = 0 dB, H = reserved; controlled through I2C when I2C_EN/PIN is high.
21	EQ_SEL/A0	input	Three-level input receive equalization pin strap when I2C_EN/PIN is low: L = fixed EQ at 7.5 dB at 3 GHz, no connect = adaptive EQ, H = fixed at 14 dB at 3 GHz; serves as I2C address bit 1 when I2C_EN/PIN is high.
22	VSADJ	input	TMDS-compliant voltage swing control nominal resistor to GND.
23	VDD	power_in	1.2 V power supply.
24	VDD	power_in	1.2 V power supply.
25	OUT_CLKn	output	TMDS data clock differential output, negative side (fail-safe main link output).
26	OUT_CLKp	output	TMDS data clock differential output, positive side (fail-safe main link output).
27	A1	input	High I2C address bit 2 for I2C programming; weak internal pull-down; leave as no connect in pin strapping mode.
28	OUT_D0n	output	TMDS data 0 differential output, negative side (fail-safe main link output).
29	OUT_D0p	output	TMDS data 0 differential output, positive side (fail-safe main link output).
30	GND	power_in	Ground.
31	OUT_D1n	output	TMDS data 1 differential output, negative side (fail-safe main link output).
32	OUT_D1p	output	TMDS data 1 differential output, positive side (fail-safe main link output).
33	HPD_SNK	input	Hot plug detect input from the sink side.
34	OUT_D2n	output	TMDS data 2 differential output, negative side (fail-safe main link output).
35	OUT_D2p	output	TMDS data 2 differential output, positive side (fail-safe main link output).
36	TX_TERM_CTL	input	Three-level transmit termination control: H = no transmit termination, L = approximately 75 to 150 Ω termination, no connect = automatic selection by data rate.
37	VDD	power_in	1.2 V power supply.
38	SCL_SNK	bidirectional	Sink-side TMDS port bidirectional DDC clock line.
39	SDA_SNK	bidirectional	Sink-side TMDS port bidirectional DDC data line.
40	NC	unconnected	No connect.
41	GND	power_in	Ground.
42	OE	input	Operation enable/reset: L = power-down mode, H = normal operation; internal weak pull-up, and the device resets on a H-to-L transition.
43	VCC	power_in	3.3 V power supply.
44	ARC_OUT	output	Audio return channel output.
45	SPDIF_IN	input	SPDIF signal input.
46	SCL_SRC	bidirectional	Source-side TMDS port bidirectional DDC clock line.
47	SDA_SRC	bidirectional	Source-side TMDS port bidirectional DDC data line.
48	VDD	power_in	1.2 V power supply.
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-48-EP(7x7)
Category	Communication Interface Chip/UART/485/232
Pins	49

CAD (KiCad official)

Symbol: TMDS181IRGZT
Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
3D model files: tmds181irgzt-etched.step / tmds181irgzt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tmds181irgzt.step / tmds181irgzt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (59 pp, sha256 80f8eef3073a8094, retrieved 2026-10-08, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF