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TMDS171RGZT
Public Made by Adomby adom
Texas Instruments Interface - Specialized, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTMDS171RGZT
Texas Instruments · Interface - Specialized · VQFN-48-EP(7x7)
TMDS171RGZT from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SWAP/POL | input | 3-level receive polarity and lane swap control: H swaps receive polarity (retimer mode only), L swaps receive lanes, and No Connect is normal operation. |
| 2 | IN_D2p | input | Channel 2 differential TMDS input (fail-safe main link); the input common-mode range is VCC − 0.4 V to VCC + 0.1 V. |
| 3 | IN_D2n | input | Channel 2 differential TMDS input (fail-safe main link); the input common-mode range is VCC − 0.4 V to VCC + 0.1 V. |
| 4 | HPD_SRC | output | Hot plug detect output to the source side. |
| 5 | IN_D1p | input | Channel 1 differential TMDS input (fail-safe main link); the input common-mode range is VCC − 0.4 V to VCC + 0.1 V. |
| 6 | IN_D1n | input | Channel 1 differential TMDS input (fail-safe main link); the input common-mode range is VCC − 0.4 V to VCC + 0.1 V. |
| 7 | GND | power_in | Ground. |
| 8 | IN_D0p | input | Channel 0 differential TMDS input (fail-safe main link); the input common-mode range is VCC − 0.4 V to VCC + 0.1 V. |
| 9 | IN_D0n | input | Channel 0 differential TMDS input (fail-safe main link); the input common-mode range is VCC − 0.4 V to VCC + 0.1 V. |
| 10 | I2C_EN/PIN | input | High puts the device in I2C control mode; low puts it in pin-strap mode. |
| 11 | IN_CLKp | input | Clock differential TMDS input (fail-safe main link); the input common-mode range is VCC − 0.4 V to VCC + 0.1 V. |
| 12 | IN_CLKn | input | Clock differential TMDS input (fail-safe main link); the input common-mode range is VCC − 0.4 V to VCC + 0.1 V. |
| 13 | VCC | power_in | 3.3 V power supply (3.135 V to 3.465 V, nominal 3.3 V). |
| 14 | VDD | power_in | 1.2 V power supply (1.1 V to 1.27 V, nominal 1.2 V). |
| 15 | SCL_CTL | bidirectional | I2C clock signal used when I2C_EN/PIN is high; it is not changed by I2C when I2C_EN/PIN is low. |
| 16 | SDA_CTL | bidirectional | I2C data signal used when I2C_EN/PIN is high; it is not changed by I2C when I2C_EN/PIN is low. |
| 17 | SIG_EN | input | Signal detector enable: L disables the signal detect circuit with termination always connected (default), and H enables it so that the device enters standby when no valid clock is present; internal weak pull-down. |
| 18 | NC | unconnected | No connect. |
| 19 | GND | power_in | Ground. |
| 20 | PRE_SEL | input | 3-level de-emphasis control when I2C_EN/PIN is low: L = −2 dB, No Connect = 0 dB, H = reserved; controlled through I2C when I2C_EN/PIN is high. |
| 21 | EQ_SEL/A0 | input | 3-level receive equalization strap when I2C_EN/PIN is low: L = fixed 7.5 dB, No Connect = adaptive EQ, H = fixed 14 dB; address bit 1 when I2C_EN/PIN is high. |
| 22 | VSADJ | input | TMDS output voltage swing control; nominal 7.06 kΩ (1%) resistor to GND. |
| 23 | VDD | power_in | 1.2 V power supply (1.1 V to 1.27 V, nominal 1.2 V). |
| 24 | VDD | power_in | 1.2 V power supply (1.1 V to 1.27 V, nominal 1.2 V). |
| 25 | OUT_CLKn | output | Clock differential TMDS output (fail-safe main link). |
| 26 | OUT_CLKp | output | Clock differential TMDS output (fail-safe main link). |
| 27 | A1 | input | High address bit 2 for I2C programming with an internal weak pull-down; leave as No Connect when I2C_EN/PIN is low. |
| 28 | OUT_D0n | output | TMDS data 0 differential output (fail-safe main link). |
| 29 | OUT_D0p | output | TMDS data 0 differential output (fail-safe main link). |
| 30 | GND | power_in | Ground. |
| 31 | OUT_D1n | output | TMDS data 1 differential output (fail-safe main link). |
| 32 | OUT_D1p | output | TMDS data 1 differential output (fail-safe main link). |
| 33 | HPD_SNK | input | Hot plug detect input from the sink side. |
| 34 | OUT_D2n | output | TMDS data 2 differential output (fail-safe main link). |
| 35 | OUT_D2p | output | TMDS data 2 differential output (fail-safe main link). |
| 36 | TX_TERM_CTL | input | 3-level transmit termination control: H = no transmit termination, L = reserved, No Connect = automatic selection (150-300 Ω differential near-end termination for 2 Gbps < DR ≤ 3.4 Gbps, none below 2 Gbps). |
| 37 | VDD | power_in | 1.2 V power supply (1.1 V to 1.27 V, nominal 1.2 V). |
| 38 | SCL_SNK | bidirectional | Sink-side TMDS port bidirectional DDC clock line. |
| 39 | SDA_SNK | bidirectional | Sink-side TMDS port bidirectional DDC data line. |
| 40 | NC | unconnected | No connect. |
| 41 | GND | power_in | Ground. |
| 42 | OE | input | Operation enable/reset: L = power-down mode, H = normal operation; internal weak pull-up, and a H-to-L transition resets the device. |
| 43 | VCC | power_in | 3.3 V power supply (3.135 V to 3.465 V, nominal 3.3 V). |
| 44 | ARC_OUT | output | Audio return channel output. |
| 45 | SPDIF_IN | input | S/PDIF signal input for the audio return channel. |
| 46 | SCL_SRC | bidirectional | Source-side TMDS port bidirectional DDC clock line. |
| 47 | SDA_SRC | bidirectional | Source-side TMDS port bidirectional DDC data line. |
| 48 | VDD | power_in | 1.2 V power supply (1.1 V to 1.27 V, nominal 1.2 V). |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-48-EP(7x7) |
| Category | Interface |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
TMDS171RGZT - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
tmds171rgzt-etched.step/tmds171rgzt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tmds171rgzt.step/tmds171rgzt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (63 pp, sha256
f4e095e1a42e2b25, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).