# TMC6200-TA-T

**TRINAMIC Motion Control GmbH** · Motor Driver ICs · TQFP-48-EP(7x7)

TMC6200-TA-T from TRINAMIC Motion Control GmbH, in a TQFP-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CU | passive | Bootstrap capacitor positive connection, tied to the U terminal using a 470nF to 1µF, 16V or 25V ceramic capacitor. |
| 2 | N.C. | unconnected | Unused pin for increased creeping distances. |
| 3 | LSW | output | Low side gate driver output for phase W. |
| 4 | LSV | output | Low side gate driver output for phase V. |
| 5 | LSU | output | Low side gate driver output for phase U. |
| 6 | 12VOUT | power_out | Output of internal 11.5V gate voltage regulator and supply of low side gate drivers; attach 2.2µF to 22µF ceramic capacitor to GND plane, or tie VSA and 12VOUT to an external gate supply. |
| 7 | 5VOUT | power_out | Output of internal 5V regulator; attach 2.2µF to 10µF ceramic capacitor to GNDA near the pin. |
| 8 | GNDA | power_in | Analog GND, connect to GND plane near the pin. |
| 9 | CURU | output | Analog output of current sense amplifier for phase U. |
| 10 | CURV | output | Analog output of current sense amplifier for phase V. |
| 11 | CURW | output | Analog output of current sense amplifier for phase W. |
| 12 | VOFS/TEST | input | Analog center reference for current sense amplifiers; leave open for 5VOUT/3 offset voltage. |
| 13 | CSN_IDRV0 | input | SPI chip select input, negative active (SPE=1), or gate driver current LSB configuration input (SPE=0). |
| 14 | SCK_IDRV1 | input | SPI serial clock input (SPE=1) or gate driver current MSB configuration input (SPE=0). |
| 15 | SDI_AMPLx10 | input | SPI data input (SPE=1) or current sense amplifier 5x or 10x amplification configuration input (SPE=0). |
| 16 | SDO_SINGLE | tri_state | SPI data output, tristate (SPE=1), or internal bridge control mode configuration input (0: dual line, 1: xH=phase polarity, xL=phase enable) (SPE=0). |
| 17 | UH | input | High side control input for phase U (or bridge polarity in single mode), with pulldown resistor. |
| 18 | UL | input | Low side control input for phase U (or bridge enable in single mode), with pulldown resistor. |
| 19 | VCC_IO | power_in | 3.3V to 5V IO supply voltage for all digital pins. |
| 20 | VH | input | High side control input for phase V (or bridge polarity in single mode), with pulldown resistor. |
| 21 | VL | input | Low side control input for phase V (or bridge enable in single mode), with pulldown resistor. |
| 22 | WH | input | High side control input for phase W (or bridge polarity in single mode), with pulldown resistor. |
| 23 | WL | input | Low side control input for phase W (or bridge enable in single mode), with pulldown resistor. |
| 24 | CLK | input | Clock input; tie to GND using a short wire for internal clock or supply an external clock, with clock-fail over circuit protecting against loss of external clock. |
| 25 | SPE | input | Mode selection input with integrated pulldown: low selects standalone mode with SPI pins as configuration pins, high enables the SPI interface. |
| 26 | FAULT | output | Diagnostics output, high upon driver error condition; clear by cycling the enable. |
| 27 | DRV_EN | input | Positive active enable input; the power stage is switched off (all motor outputs floating) when driven low, and cycling low clears FAULT. |
| 28 | N.C. | unconnected | Unused pin for increased creeping distances. |
| 29 | VSA | power_in | Analog supply voltage for the 11.5V and 5V regulators, normally tied to VS, with a 100nF filtering capacitor to GND. |
| 30 | CPO | passive | Charge pump capacitor output. |
| 31 | N.C. | unconnected | Unused pin for increased creeping distances. |
| 32 | CPI | passive | Charge pump capacitor input, tied to CPO using a 22nF 100V capacitor, with optional 10-22Ohm series resistor if supply ringing is considerable. |
| 33 | VS | power_in | Motor supply voltage, must be tied to the positive bridge supply voltage with filtering capacity near the pin and short loop to GND plane. |
| 34 | VCP | passive | Charge pump voltage, tied to VS using a 100nF capacitor. |
| 35 | N.C. | unconnected | Unused pin for increased creeping distances. |
| 36 | CW | passive | Bootstrap capacitor positive connection, tied to the W terminal using 470nF to 1µF, 16V or 25V ceramic capacitor. |
| 37 | HSW | output | High side gate driver output for phase W. |
| 38 | W | passive | Bridge center and bootstrap capacitor negative connection, connected to the source pin of the HS-MOSFET. |
| 39 | WSENSE | input | Analog sense resistor connection for phase W on the motor side of the sense resistor, with 10Ω to 22Ω protection resistor recommended, or directly to W if no sense resistor is used. |
| 40 | N.C. | unconnected | Unused pin for increased creeping distances. |
| 41 | VSENSE | input | Analog sense resistor connection for phase V on the motor side of the sense resistor, with 10Ω to 22Ω protection resistor recommended, or directly to V if no sense resistor is used. |
| 42 | V | power_in | Bridge center and bootstrap capacitor negative connection, connected to the source pin of the HS-MOSFET. |
| 43 | HSV | output | High side gate driver output for phase V. |
| 44 | CV | passive | Bootstrap capacitor positive connection, tied to the V terminal using 470nF to 1µF, 16V or 25V ceramic capacitor. |
| 45 | N.C. | unconnected | Unused pin for increased creeping distances. |
| 46 | USENSE | input | Analog sense resistor connection for phase U on the motor side of the sense resistor, with 10Ω to 22Ω protection resistor recommended, or directly to U if no sense resistor is used. |
| 47 | U | passive | Bridge center and bootstrap capacitor negative connection, connected to the source pin of the HS-MOSFET. |
| 48 | HSU | output | High side gate driver output for phase U. |
| 49 | EP | power_in | Exposed die pad (GNDP, GNDD) connected to a GND plane with many vias; serves as GND for the low side gate drivers and digital logic. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | TRINAMIC Motion Control GmbH |
| Package | TQFP-48-EP(7x7) |
| Category | Power Management ICs |
| Pins | 49 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage operating with inductive load | VVS, VVSA | -0.5 |  | 65 | V |  | 35 |
| Supply and bridge voltage short time peak | VVSMAX |  |  | 70 | V | limited by peak voltage on charge pump output and Cxx pins | 35 |
| VSA supply voltage | VVSAMAX | -0.5 |  | 65 | V |  | 35 |
| Peak voltages on Cxx bootstrap pins and VCP | VCxCP |  |  | 85 | V |  | 35 |
| Supply voltage V12 | V12VOUT | -0.5 |  | 15 | V |  | 35 |
| Peak voltages on U/V/W pins | VX | -6 |  | 6 | V | max printed as VVS+6 V (due to stray inductivity) | 35 |
| Peak voltages on Cxx bootstrap pins relative to BM | VCxx | -0.5 |  | 16 | V |  | 35 |
| I/O supply voltage | VVIO | -0.5 |  | 5.5 | V |  | 35 |
| Supply voltage (5VOUT) | V5VOUT | -0.5 |  | 5.5 | V |  | 35 |
| Logic input voltage | VI | -0.5 |  | 0.5 | V | max printed as VVIO+0.5 V | 35 |
| Maximum current to/from digital pins and analog low voltage I/Os | IIO | -500 |  | 500 | mA | short time peak current | 35 |
| Maximum differential input voltage for current amplifier | VX-VSENSEX | -1.5 |  | 1.5 | V |  | 35 |
| Maximum short time input current for current amplifier | ISENSEX | -200 |  | 200 | mA |  | 35 |
| 5V regulator output current | I5VOUT |  |  | 30 | mA | internal plus external load | 35 |
| 5V regulator continuous power dissipation | P5VOUT |  |  | 1 | W | (VVSA-5V) * I5VOUT | 35 |
| 12V regulator output current | I12VOUT |  |  | 20 | mA | internal plus external load | 35 |
| 12V regulator continuous power dissipation | P12VOUT |  |  | 0.5 | W | (VVM-5V) * I5VOUT | 35 |
| Junction temperature | TJ | -50 |  | 150 | °C |  | 35 |
| Storage temperature | TSTG | -55 |  | 150 | °C |  | 35 |
| ESD protection for interface pins (HBM) | VESDAP |  |  | 4 | kV | Human body model | 35 |
| ESD protection for handling (HBM) | VESD |  |  | 1 | kV | Human body model | 35 |
| Junction temperature (operational) | TJ | -40 |  | 125 | °C |  | 35 |
| Supply voltage for motor and bridge | VVS | 10 |  | 60 | V |  | 35 |
| Supply voltage VSA | VVSA | 10 |  | 60 | V |  | 35 |
| Supply voltage for VSA and 12OUT (internal gate voltage regulator bridged) | V12VOUT, VVSA | 10 |  | 13 | V |  | 35 |
| Lower supply voltage (reduced spec) | VVS | 8 |  |  | V | short to GND protection not functional, lower limit depending on MOSFETs gate threshold voltage and load current | 35 |
| I/O supply voltage | VVIO | 3 |  | 5.25 | V |  | 35 |
| Total supply current, driver disabled | IS |  | 11 | 15 | mA | VVS = VVSA = 24.0V, internal clock | 36 |
| IO supply current | IVIO |  | 15 | 30 | µA | no load on outputs, inputs at VIO or GND; excludes pullup/pull-down resistors | 36 |
| RDSON lowside off driver | RONL |  | 1 | 1.6 | Ω | Gate off, VVS = 24.0V; Tj=50°C | 36 |
| RDSON highside off driver | RONH |  | 1.3 | 2 | Ω | Gate off, VVS = 24.0V; Tj=50°C | 36 |
| Minimum effective BBM time | tBBM0 | 30 | 50 | 70 | ns | Individual LS and HS signals (singleline=0) | 36 |
| Reaction delay time LS/HS input to gate driver output change | tDLY | 65 | 85 | 110 | ns | Individual LS and HS signals (singleline=0) | 36 |
| Matching difference of gate driver reaction delay times | tDLYMATCH |  |  | 10 | ns | Individual LS and HS signals (singleline=0) | 36 |
| Charge pump voltage threshold for undervoltage detection | VVCP-VVS | 4.5 | 5.5 | 6.5 | V | rising, using internal 5V regulator voltage | 37 |
| 5V regulator output voltage | V5VOUT | 4.8 | 5 | 5.2 | V | TJ = 25°C, VVS = VVSA = 24.0V | 37 |
| Deviation of 5V output over full temperature range | V5VOUT(DEV) |  | 5 | 50 | mV | drivers disabled, TJ = full range (printed +/-5, +/-50) | 37 |
| Deviation of 5V output over supply voltage | V5VOUT(DEV) |  | 20 |  | mV / 10V | drivers disabled, internal clock, TA = 25°C, VVSA = 10V to 30V (printed +/-20) | 37 |
| 12V regulator output voltage | V12VOUT | 10.8 | 11.5 | 12.2 | V | operating, internal clock, TJ = 25°C | 37 |
| Clock oscillator frequency | fCLKOSC | 23 | 24 | 25 | MHz | tJ=50°C | 37 |
| External clock frequency (operating) | fCLK | 4 |  | 16 | MHz | 40%..60% dutycycle for typ. 50% for max.; typ printed as 10-13.4 | 37 |
| External clock high / low level time | tCLKH / tCLKL | 10 |  |  | ns | CLK driven to 0.1 VVIO / 0.9 VVIO | 37 |
| External clock timeout detection | tCLKH1 | 32 |  | 48 | cycles | CLK driven high, in cycles of internal fCLKOSC | 37 |
| Short detector delay | tSD0 | 0.5 | 0.85 | 1.1 | µs | FILT_ISENSE=0, S2xx_LEVEL=6, shortdelay=0, including 100ns filtering time | 38 |
| Short detector delay | tSD1 | 1.1 | 1.6 | 2.2 | µs | shortdelay=1 | 38 |
| Short detector level S2VS | VBM | 1.4 | 1.56 | 1.72 | V | S2VS_LEVEL=15 | 38 |
| Short detector level S2VS | VBM | 0.55 | 0.625 | 0.7 | V | S2VS_LEVEL=6 | 38 |
| Short detector level S2G | VS - VBM | 1.3 | 1.56 | 1.85 | V | S2G_LEVEL=15, VS<52V | 38 |
| Short detector level S2G | VS - VBM | 0.46 | 0.625 | 0.85 | V | S2G_LEVEL=6, VS<52V | 38 |
| VVSA undervoltage threshold for RESET | VUV_VSA | 3.8 | 4.2 | 4.6 | V | VVSA rising | 38 |
| VVCC_IO undervoltage threshold for RESET | VUV_VIO | 2 | 2.2 | 3 | V | VVCC_IO rising (delay typ. 10µs) | 38 |
| Overtemperature prewarning 120°C | TOTPW | 100 | 120 | 140 | °C | Temperature rising | 38 |
| Overtemperature shutdown 150°C | TOT150 | 135 | 150 | 170 | °C | Temperature rising | 38 |
| Amplification (amplification=0) | AAMPL | 4.85 | 5 | 5.15 | V/V | amplification=0, Tj=50°C | 39 |
| Amplification absolute tolerance | AABSTOL | -3 |  | 3 | % | Tj=50°C | 39 |
| Amplification matching between channels | AMATCH | -2 |  | 2 | % | Tested at 1/2 full scale | 39 |
| Offset voltage variation over sense input voltage (output) | VOFSVAR | -10 | 0 | 10 | mV | Vsense=0V to 50V, amplification=0 | 39 |
| Current amplifier output offset voltage, amplification=0 | VOFS | -130 |  | 130 | mV | amplification=0 | 39 |
| Sense amplifier output resistance | RCUR | 36 | 56 | 76 | Ω | Tj=50°C | 39 |
| Input Resistance VOFS pin | RVOFS | 130 | 165 | 210 | kΩ | Tj=50°C | 39 |
| Junction to ambient thermal resistance | RTMJA |  | 21 |  | K/W | 2s2p JEDEC EIA JESD51-5 and JESD51-7 board | 40 |

## CAD (KiCad official)

- Symbol: `TMC6200-TA-T`
- Footprint: `Package_QFP:TQFP-48-1EP_7x7mm_P0.5mm_EP5x5mm`
- 3D model: TQFP-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files: `tmc6200-ta-t-etched.step` / `tmc6200-ta-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tmc6200-ta-t.step` / `tmc6200-ta-t.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [TRINAMIC Motion Control GmbH datasheet](docs/tmc6200-ta-t-datasheet.pdf) (47 pp, sha256 `dfabdf8d076d0cf3`, retrieved 2026-10-23, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tmc6200-ta-t-datasheet.pdf)