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TM80N06NF
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Tritech MOS MOSFETs, DFN5x6-8L. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TM80N06NF
Tritech MOS · MOSFETs · DFN5x6-8L
TM80N06NF from Tritech MOS, in a DFN5x6-8L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source of the N-channel MOSFET, shown on the package top view as one of three source pins S S S next to the gate. |
| 2 | S | passive | Source of the N-channel MOSFET, shown on the package top view as one of three source pins S S S next to the gate. |
| 3 | S | passive | Source of the N-channel MOSFET, shown on the package top view as one of three source pins S S S next to the gate. |
| 4 | G | input | Gate of the N-channel MOSFET with a Gate-Source voltage rating of ±25 V and a threshold of 2 to 4 V. |
| 5 | D | passive | Drain of the N-channel MOSFET (VDS 60 V, ID 80 A), one of four drain pins D D D D on the opposite edge from the source and gate pins. |
| 6 | D | passive | Drain of the N-channel MOSFET (VDS 60 V, ID 80 A), one of four drain pins D D D D on the opposite edge from the source and gate pins. |
| 7 | D | passive | Drain of the N-channel MOSFET (VDS 60 V, ID 80 A), one of four drain pins D D D D on the opposite edge from the source and gate pins. |
| 8 | D | passive | Drain of the N-channel MOSFET (VDS 60 V, ID 80 A), one of four drain pins D D D D on the opposite edge from the source and gate pins. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Tritech MOS |
| Package | DFN5x6-8L |
| Category | Transistors/Thyristors |
| Pins | 9 |
CAD (KiCad official)
- Symbol:
TM80N06NF - Footprint:
Package_DFN_QFN:DFN-S-8-1EP_6x5mm_P1.27mm - 3D model: DFN5x6-8L (KiCad packages3D, STEP)
- 3D model files:
tm80n06nf-etched.step/tm80n06nf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tm80n06nf.step/tm80n06nf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Tritech MOS datasheet (7 pp, sha256
f2a832b9dbda3d28, retrieved 2026-10-09, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TM80N06NF
**Tritech MOS** · MOSFETs · DFN5x6-8L
TM80N06NF from Tritech MOS, in a DFN5x6-8L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source of the N-channel MOSFET, shown on the package top view as one of three source pins S S S next to the gate. |
| 2 | S | passive | Source of the N-channel MOSFET, shown on the package top view as one of three source pins S S S next to the gate. |
| 3 | S | passive | Source of the N-channel MOSFET, shown on the package top view as one of three source pins S S S next to the gate. |
| 4 | G | input | Gate of the N-channel MOSFET with a Gate-Source voltage rating of ±25 V and a threshold of 2 to 4 V. |
| 5 | D | passive | Drain of the N-channel MOSFET (VDS 60 V, ID 80 A), one of four drain pins D D D D on the opposite edge from the source and gate pins. |
| 6 | D | passive | Drain of the N-channel MOSFET (VDS 60 V, ID 80 A), one of four drain pins D D D D on the opposite edge from the source and gate pins. |
| 7 | D | passive | Drain of the N-channel MOSFET (VDS 60 V, ID 80 A), one of four drain pins D D D D on the opposite edge from the source and gate pins. |
| 8 | D | passive | Drain of the N-channel MOSFET (VDS 60 V, ID 80 A), one of four drain pins D D D D on the opposite edge from the source and gate pins. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Tritech MOS |
| Package | DFN5x6-8L |
| Category | Transistors/Thyristors |
| Pins | 9 |
## CAD (KiCad official)
- Symbol: `TM80N06NF`
- Footprint: `Package_DFN_QFN:DFN-S-8-1EP_6x5mm_P1.27mm`
- 3D model: DFN5x6-8L (KiCad packages3D, STEP)
- 3D model files: `tm80n06nf-etched.step` / `tm80n06nf-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tm80n06nf.step` / `tm80n06nf.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Tritech MOS datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590908426165960704) (7 pp, sha256 `f2a832b9dbda3d28`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tm80n06nf-datasheet.pdf)