# TM7706-SOP16

**TM(Shenzhen Titan Micro Elec)** · Analog To Digital Converters (ADC) · SOP-16

TM7706-SOP16 from TM(Shenzhen Titan Micro Elec), in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SCLK | input | Serial clock input for reading and writing the on-chip registers. |
| 2 | XI | input | Clock input for a crystal or external clock; fCLKIN is 400 kHz min to 2500 kHz max. |
| 3 | XO | output | Clock output for the crystal oscillator; goes low when OSCDIS is set to reduce power. |
| 4 | CSN | input | Active-low chip select; must be pulled low to read or write registers and pulled high afterward. |
| 5 | RESET | input | Active-low reset that resets all logic, the digital filter and the analog modulator to default state; pulse width tR is at least 100 ns. |
| 6 | AIN1 | input | Analog input of channel 1, pseudo-differential and referenced to COMMON. |
| 7 | AIN2 | input | Analog input of channel 2, pseudo-differential and referenced to COMMON. |
| 8 | COMMON | input | Common input that is the reference point for analog channels 1, 2 and 3. |
| 9 | REF INP | input | Positive reference voltage input; REF INP must be higher than REF INN, with 2.5 V at 5 V supply or 1.225 V at 3 V supply. |
| 10 | REF INN | input | Negative reference voltage input, connected to GND in the electrical characteristics test conditions. |
| 11 | AIN3 | input | Analog input of channel 3, referenced to COMMON (the pin table lists it as the negative differential input). |
| 12 | OKL | output | Logic output flag that is low when the ADC conversion is complete and data can be read, and high while converting or updating. |
| 13 | DOUT | output | Serial data output, with data shifted out on the falling edge of SCLK, MSB first. |
| 14 | DIN | input | Serial data input, with data written on the rising edge of SCLK, MSB first. |
| 15 | VDD | power_in | Power supply of 3 V or 5 V with ±5% range; absolute maximum is -0.3 V to 7 V. |
| 16 | GND | power_in | System ground. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | TM(Shenzhen Titan Micro Elec) |
| Package | SOP-16 |
| Category | Data Acquisition |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Main clock frequency | fCLKIN | 400 |  | 2500 | kHz |  | 4 |
| Clock low time | Tlow | 0.4 |  |  | *tCLKIN | tCLKIN=1/fCLKIN | 4 |
| Clock high time | Thigh | 0.4 |  |  | *tCLKIN | tCLKIN=1/fCLKIN | 4 |
| OKL high pulse | tO | 500 |  |  | *tCLKIN |  | 4 |
| RESET pulse width | tR | 100 |  |  | ns |  | 4 |
| CSN fall to first SCLK rise | Tcsn1 | 120 |  |  | ns |  | 4 |
| SCLK fall to DIN valid interval | tdo | 0 |  | 80 | ns | VDD=5V | 4 |
| SCLK fall to DIN valid interval | tdo | 0 |  | 100 | ns | VDD=3V | 4 |
| SCLK rise to CSN rise | Tcsn2 | 0 |  |  | ns |  | 4 |
| Bus release time after SCLK rise | tsout | 10 |  | 60 | ns | VDD=5V | 4 |
| Bus release time after SCLK rise | tsout |  |  | 100 | ns | VDD=3V | 4 |
| DIN valid to SCLK rise setup | tds | 30 |  |  | ns |  | 4 |
| DIN valid to SCLK rise hold | tdh | 20 |  |  | ns |  | 4 |
| OKL fall to CSN fall | toc | 0 |  |  | ns |  | 4 |
| Clock pulse width high (low) | tspw | 100 |  |  | ns |  | 4 |
| Logic supply voltage | VDD | -0.3 |  | 7 | V | TA=+25°C | 9 |
| Analog/digital input voltage | Vin | -0.3 |  |  | V | max is VDD+0.3 | 9 |
| Digital output voltage | Vout | -0.3 |  |  | V | max is VDD+0.3 | 9 |
| Operating temperature range | Topr | -40 |  | 85 | °C |  | 9 |
| Storage temperature range | Tstg | -65 |  | 150 | °C |  | 9 |
| Junction temperature | Tj |  |  | 150 | °C |  | 9 |
| ESD human body model |  |  |  | 4000 | V | HBM | 9 |
| Integral nonlinearity |  | -0.003 |  | 0.003 | % of FSR | VDD=3V or 5V, TA=25°C | 9 |
| Bipolar negative full-scale error |  | 0 | 0.001 | 0.003 | % of FSR/°C |  | 10 |
| REF IN absolute/common-mode voltage |  | 0 |  |  | V | max is VDD | 10 |
| AIN absolute/common-mode voltage |  | -0.03 |  |  | V | BUFEN=0; max is VDD+0.03 | 10 |
| AIN absolute/common-mode voltage |  | 0.05 |  |  | V | BUFEN=1; max is VDD-1.5 | 10 |
| REFINP-REFINN voltage |  | 1 |  | 1.75 | V | VDD=3V, Vref=1.225V | 10 |
| REFINP-REFINN voltage |  | 1 |  | 3.5 | V | VDD=5V, Vref=2.5V | 10 |
| Input low voltage (except SCLK and XI) | VIL |  |  | 0.8 | V | VDD=5V | 10 |
| Input low voltage (except SCLK and XI) | VIL |  |  | 0.4 | V | VDD=3V | 10 |
| Input high voltage (except SCLK and XI) | VIH | 2 |  |  | V |  | 10 |
| SCLK positive threshold | VT+ | 1.4 |  | 3 | V | VDD=5V | 10 |
| SCLK negative threshold | VT- | 0.8 |  | 1.4 | V | VDD=5V | 10 |
| SCLK hysteresis | VT+ - VT- | 0.4 |  | 0.8 | V | VDD=5V | 10 |
| SCLK positive threshold | VT+ | 1 |  | 2.5 | V | VDD=3V | 10 |
| SCLK negative threshold | VT- | 0.4 |  | 1.1 | V | VDD=3V | 10 |
| SCLK hysteresis | VT+ - VT- | 0.375 |  | 0.8 | V | VDD=3V | 10 |
| XI input low level |  |  |  | 0.8 | V | VDD=5V | 10 |
| XI input high level |  | 3.5 |  |  | V | VDD=5V | 10 |
| XI input low level |  |  |  | 0.4 | V | VDD=3V | 10 |
| XI input high level |  | 2.5 |  |  | V | VDD=3V | 10 |
| Supply current |  |  |  | 0.32 | mA | VDD=3V, BUFEN=0, fCLKIN=1MHz, gain 1-128 | 11 |
| Supply current |  |  |  | 0.6 | mA | VDD=3V, BUFEN=1, fCLKIN=1MHz, gain 1-128 | 11 |
| Supply current |  |  |  | 0.4 | mA | VDD=3V, BUFEN=0, fCLKIN=2.4576MHz, gain 1-4 | 11 |
| Supply current |  |  |  | 0.7 | mA | VDD=3V, BUFEN=1, fCLKIN=2.4576MHz, gain 1-4 | 11 |
| Supply current |  |  |  | 1.1 | mA | VDD=3V, BUFEN=1, fCLKIN=2.4576MHz, gain 8-128 | 11 |
| Supply current |  |  |  | 0.45 | mA | VDD=5V, BUFEN=0, fCLKIN=1MHz, gain 1-128 | 11 |
| Supply current |  |  |  | 0.85 | mA | VDD=5V, BUFEN=0, fCLKIN=2.4576MHz, gain 8-128 | 11 |
| Supply current |  |  |  | 0.9 | mA | VDD=5V, BUFEN=1, fCLKIN=2.4576MHz, gain 1-4 | 11 |
| Supply current |  |  |  | 1.3 | mA | VDD=5V, BUFEN=1, fCLKIN=2.4576MHz, gain 8-128 | 11 |
| Power-down current |  |  |  | 16 | uA | VDD=5V, XI=0V/VDD | 11 |
| Power-down current |  |  |  | 8 | uA | VDD=3V, XI=0V/VDD | 11 |
| Power supply rejection ratio |  |  | 86 |  | dB | VDD=3V, gain 1 | 11 |
| Power supply rejection ratio |  |  | 93 |  | dB | VDD=3V, gain 8-128 | 11 |
| Power supply rejection ratio |  |  | 90 |  | dB | VDD=5V, gain 1 | 11 |
| Power supply rejection ratio |  |  | 91 |  | dB | VDD=5V, gain 8-128 | 11 |

## CAD (KiCad official)

- Symbol: `TM7706-SOP16`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files: `tm7706-sop16-etched.step` / `tm7706-sop16-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tm7706-sop16.step` / `tm7706-sop16.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [TM(Shenzhen Titan Micro Elec) datasheet](docs/tm7706-sop16-datasheet.pdf) (15 pp, sha256 `529a5ed0fbe14740`, retrieved 2026-10-24, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tm7706-sop16-datasheet.pdf)