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TM7705-DIP16
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TM Shenzhen Titan Micro Elec Analog To Digital Converters (ADC), DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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PCB Footprint
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Datasheet
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README
markdownTM7705-DIP16
TM Shenzhen Titan Micro Elec · Analog To Digital Converters (ADC) · DIP-16
TM7705-DIP16 from TM Shenzhen Titan Micro Elec, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SCLK | input | Serial read/write clock input; DIN is written on its rising edge and DOUT is output on its falling edge, with MSB first. |
| 2 | XI | input | Clock input for the crystal or an external clock; the datasheet specifies fCLKIN from 400 kHz to 2500 kHz. |
| 3 | XO | output | Clock output for the crystal; when OSCDIS is set to 1, XO is held low to reduce power consumption. |
| 4 | CSN | input | Active-low chip select; registers can only be read or written while CSN is low, and CSN must be pulled high after the transfer. |
| 5 | RESET | input | Active-low reset; pulling it low resets the logic, digital filter and modulator and returns the registers to default states, with a minimum pulse width of 100 ns. |
| 6 | AIN2P | input | Differential analog positive input for channel 2; the absolute/common-mode range is -0.03 V to VDD+0.03 V with BUFEN=0 and 0.05 V to VDD-1.5 V with BUFEN=1. |
| 7 | AIN1P | input | Differential analog positive input for channel 1; the absolute/common-mode range is -0.03 V to VDD+0.03 V with BUFEN=0 and 0.05 V to VDD-1.5 V with BUFEN=1. |
| 8 | AIN1N | input | Differential analog negative input for channel 1; the absolute/common-mode range is -0.03 V to VDD+0.03 V with BUFEN=0 and 0.05 V to VDD-1.5 V with BUFEN=1. |
| 9 | REF INP | input | Positive reference voltage input, which must be greater than REF INN; the reference is +2.5 V at 5 V supply or +1.225 V at 3 V supply, and the REF IN voltage range is 0 to VDD. |
| 10 | REF INN | input | Negative reference voltage input, which must be less than REF INP; the REF IN voltage range is 0 to VDD and the electrical characteristics assume REF INN = GND. |
| 11 | AIN2N | input | Differential analog negative input for channel 2; the absolute/common-mode range is -0.03 V to VDD+0.03 V with BUFEN=0 and 0.05 V to VDD-1.5 V with BUFEN=1. |
| 12 | OKL | output | Conversion-complete indicator; low means the ADC result register is updated and can be read, high means conversion or update is in progress and data cannot be read. |
| 13 | DOUT | output | Serial data output; data is shifted out on the falling edge of SCLK, MSB first. |
| 14 | DIN | input | Serial data input; data is written on the rising edge of SCLK, with data setup of at least 30 ns and hold of at least 20 ns. |
| 15 | VDD | power_in | Supply voltage of 3 V or 5 V (±5%); the absolute maximum rating is -0.3 V to 7 V. |
| 16 | GND | power_in | System ground. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TM Shenzhen Titan Micro Elec |
| Package | DIP-16 |
| Category | Data Acquisition |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Logic supply voltage | VDD | -0.3 | 7 | V | 9 | ||
| Analog input voltage | Vin | -0.3 | V | 9 | |||
| Digital output voltage | Vout | -0.3 | V | 9 | |||
| Operating temperature range | Topr | -40 | 85 | ℃ | 9 | ||
| Storage temperature range | Tstg | -65 | 150 | ℃ | 9 | ||
| Junction temperature | Tj | 150 | ℃ | 9 | |||
| ESD human body model (HBM) | ESD | 4000 | V | Human body model (HBM) | 9 | ||
| Supply voltage tolerance (3V or 5V nominal) | VDD | -5 | 5 | % | Nominal 3V or 5V supply (feature list) | 1 | |
| Integral nonlinearity | -0.003 | 0.003 | %of FSR | 9 | |||
| Bipolar negative full-scale error | -0.003 | 0.003 | %of FSR/℃ | 10 | |||
| REF IN absolute/common-mode voltage | 0 | V | 10 | ||||
| AIN absolute/common-mode voltage | -0.03 | V | BUFEN=0 | 10 | |||
| AIN absolute/common-mode voltage | 0.05 | V | BUFEN=1 | 10 | |||
| AIN differential voltage, unipolar input | 0 | V | Unipolar input | 10 | |||
| REFINP-REFINN difference | 1 | 1.75 | V | VDD=3V,Vref=1.225V | 10 | ||
| REFINP-REFINN difference | 1 | 3.5 | V | VDD=5V,Vref=2.5V | 10 | ||
| Input low voltage (except SCLK and XI) | VIL | 0.8 | V | VDD=5V | 10 | ||
| Input low voltage (except SCLK and XI) | VIL | 0.4 | V | VDD=3V | 10 | ||
| Input high voltage (except SCLK and XI) | VIH | 2 | V | 10 | |||
| SCLK Schmitt trigger positive threshold VT+ | VT+ | 1.4 | 3 | V | VDD=5V | 10 | |
| SCLK Schmitt trigger negative threshold VT- | VT_ | 0.8 | 1.4 | V | VDD=5V | 10 | |
| SCLK Schmitt trigger hysteresis VT+-VT- | VT+-VT_ | 0.4 | 0.8 | V | VDD=5V | 10 | |
| SCLK Schmitt trigger positive threshold VT+ | VT+ | 1 | 2.5 | V | VDD=3V | 10 | |
| SCLK Schmitt trigger negative threshold VT- | VT_ | 0.4 | 1.1 | V | VDD=3V | 10 | |
| SCLK Schmitt trigger hysteresis VT+-VT- | VT+-VT_ | 0.375 | 0.8 | V | VDD=3V | 10 | |
| XI input low voltage | 0.8 | V | VDD=5V | 10 | |||
| XI input high voltage | 3.5 | V | VDD=5V | 10 | |||
| XI input low voltage | 0.4 | V | VDD=3V | 10 | |||
| XI input high voltage | 2.5 | V | VDD=3V | 10 | |||
| Power-down mode current | 8 | μA | VDD=3V, XI=0V / VDD. | 11 | |||
| Master clock frequency fCLKIN | fCLKIN | 400 | 2500 | kHz | 4 | ||
| Slck falling to DIN valid acquisition interval tdo | tdo | 0 | 80 | ns | VDD=5V | 4 | |
| Slck falling to DIN valid acquisition interval tdo | tdo | 0 | 100 | ns | VDD=3V | 4 | |
| Bus release time after SCLK rising tsout | tsout | 10 | 60 | ns | VDD=5V | 4 |
CAD (KiCad official)
- Symbol:
TM7705-DIP16 - Footprint:
Package_DIP:DIP-16_W7.62mm - 3D model: DIP-16 (KiCad packages3D, STEP)
- 3D model files:
tm7705-dip16-etched.step/tm7705-dip16-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tm7705-dip16.step/tm7705-dip16.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TM Shenzhen Titan Micro Elec datasheet (15 pp, sha256
ccc07c2549b56e2b, retrieved 2026-10-15, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).