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TM4C123GH6PMT7R

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Texas Instruments Microcontrollers (MCU/MPU/SOC), QFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TM4C123GH6PMT7R

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · QFP-64(10x10)

TM4C123GH6PMT7R from Texas Instruments, in a QFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PB6 bidirectional GPIO port B bit 6 (TTL); alternate functions M0PWM0 PWM output, SSI2Rx receive, and T0CCP0 16/32-bit timer capture/compare/PWM 0.
2 VDDA power_in Positive supply for the analog circuits (ADC, Analog Comparators), separated from VDD to reduce noise; must meet the Table 24-5 voltage specification regardless of system implementation.
3 GNDA power_in Ground reference for the analog circuits (ADC, Analog Comparators), separated from GND to reduce noise coupling from VDD.
4 PB7 bidirectional GPIO port B bit 7 (TTL); alternate functions M0PWM1 PWM output, SSI2Tx transmit, and T0CCP1 16/32-bit timer capture/compare/PWM 1.
5 PF4 bidirectional GPIO port F bit 4 (TTL); alternate functions IDX0 QEI0 index input, M1FAULT0 PWM1 fault input, T2CCP0 timer capture/compare/PWM 0, and USB0EPEN external power enable output.
6 PE3 bidirectional GPIO port E bit 3; analog input AIN0 to the ADC. AINx signals are not 5-V tolerant.
7 PE2 bidirectional GPIO port E bit 2; analog input AIN1 to the ADC. AINx signals are not 5-V tolerant.
8 PE1 bidirectional GPIO port E bit 1; analog input AIN2 to the ADC and U7Tx UART7 transmit output. AINx signals are not 5-V tolerant.
9 PE0 bidirectional GPIO port E bit 0; analog input AIN3 to the ADC and U7Rx UART7 receive input. AINx signals are not 5-V tolerant.
10 PD7 bidirectional GPIO port D bit 7 (TTL); alternate functions NMI non-maskable interrupt input, PhB0 QEI0 phase B, U2Tx UART2 transmit, and WT5CCP1 wide timer capture/compare/PWM 1; locked and requires unlock/commit to reprogram.
11 VDD power_in Positive supply for I/O and some logic.
12 GND power_in Ground reference for logic and I/O pins.
13 PC7 bidirectional GPIO port C bit 7 (TTL); alternate functions C0- analog comparator 0 negative input, U3Tx UART3 transmit, USB0PFLT external power-fault input in Host mode, and WT1CCP1 wide timer capture/compare/PWM 1.
14 PC6 bidirectional GPIO port C bit 6 (TTL); alternate functions C0+ analog comparator 0 positive input, PhB1 QEI1 phase B, U3Rx UART3 receive, USB0EPEN external power enable output, and WT1CCP0 wide timer capture/compare/PWM 0.
15 PC5 bidirectional GPIO port C bit 5 (TTL); alternate functions C1+ analog comparator 1 positive input, M0PWM7 PWM output, PhA1 QEI1 phase A, U1CTS, U1Tx, U4Tx, and WT0CCP1 wide timer capture/compare/PWM 1.
16 PC4 bidirectional GPIO port C bit 4 (TTL); alternate functions C1- analog comparator 1 negative input, IDX1 QEI1 index input, M0PWM6 PWM output, U1RTS, U1Rx, U4Rx, and WT0CCP0 wide timer capture/compare/PWM 0.
17 PA0 bidirectional GPIO port A bit 0 (TTL); defaults to U0Rx UART0 receive after reset, with alternate function CAN1Rx CAN1 receive.
18 PA1 bidirectional GPIO port A bit 1 (TTL); defaults to U0Tx UART0 transmit after reset, with alternate function CAN1Tx CAN1 transmit.
19 PA2 bidirectional GPIO port A bit 2 (TTL); defaults to SSI0Clk SSI0 clock after reset.
20 PA3 bidirectional GPIO port A bit 3 (TTL); defaults to SSI0Fss SSI0 frame signal after reset.
21 PA4 bidirectional GPIO port A bit 4 (TTL); defaults to SSI0Rx SSI0 receive after reset.
22 PA5 bidirectional GPIO port A bit 5 (TTL); defaults to SSI0Tx SSI0 transmit after reset.
23 PA6 bidirectional GPIO port A bit 6 (TTL); alternate functions I2C1SCL (open-drain, has active pull-up, so the port pin must not be configured as open drain) and M1PWM2 PWM output.
24 PA7 bidirectional GPIO port A bit 7 (TTL); alternate functions I2C1SDA (open-drain data line) and M1PWM3 PWM output.
25 VDDC power_out Core supply of 1.2 V from the on-chip LDO; connect only to the other VDDC pins and the external capacitor specified in Table 24-12.
26 VDD power_in Positive supply for I/O and some logic.
27 GND power_in Ground reference for logic and I/O pins.
28 PF0 bidirectional GPIO port F bit 0 (TTL); defaults to GPIO but is locked and must be unlocked via GPIOLOCK and committed via GPIOCR to reprogram; alternate functions C0o comparator 0 output, CAN0Rx, M1PWM4, NMI, PhA0, SSI1Rx, T0CCP0, and U1RTS.
29 PF1 bidirectional GPIO port F bit 1 (TTL); alternate functions C1o comparator 1 output, M1PWM5 PWM output, PhB0, SSI1Tx, T0CCP1, TRD1 trace data, and U1CTS.
30 PF2 bidirectional GPIO port F bit 2 (TTL); alternate functions M0FAULT0 PWM fault input, M1PWM6 PWM output, SSI1Clk, T1CCP0, and TRD0 trace data.
31 PF3 bidirectional GPIO port F bit 3 (TTL); alternate functions CAN0Tx, M1PWM7 PWM output, SSI1Fss, T1CCP1, and TRCLK trace clock.
32 WAKE input External TTL input that brings the processor out of Hibernate mode when asserted.
33 HIB output TTL output that indicates the processor is in Hibernate mode.
34 XOSC0 input Hibernation oscillator crystal input or external clock reference input for a 32.768-kHz crystal or oscillator; the oscillator amplitude must be below VBAT.
35 GNDX power_in Ground for the Hibernation oscillator; connect to digital ground with the crystal load capacitors, or directly to ground when using an external oscillator.
36 XOSC1 output Hibernation oscillator crystal output; leave unconnected when using a single-ended clock source.
37 VBAT power_in Power source for the Hibernation module, normally connected to the positive terminal of a battery as battery backup supply.
38 RST input TTL system reset input.
39 GND power_in Ground reference for logic and I/O pins.
40 OSC0 input Main oscillator crystal input or external clock reference input (analog).
41 OSC1 output Main oscillator crystal output; leave unconnected when using a single-ended clock source.
42 VDD power_in Positive supply for I/O and some logic.
43 PD4 bidirectional GPIO port D bit 4, not 5-V tolerant; alternate functions U6Rx UART6 receive, USB0DM USB D- differential data, and WT4CCP0 wide timer capture/compare/PWM 0.
44 PD5 bidirectional GPIO port D bit 5, not 5-V tolerant; alternate functions U6Tx UART6 transmit, USB0DP USB D+ differential data, and WT4CCP1 wide timer capture/compare/PWM 1.
45 PB0 bidirectional GPIO port B bit 0, not 5-V tolerant; alternate functions T2CCP0 timer capture/compare/PWM 0, U1Rx UART1 receive, and USB0ID analog USB ID sense input.
46 PB1 bidirectional GPIO port B bit 1, not 5-V tolerant; alternate functions T2CCP1 timer capture/compare/PWM 1, U1Tx UART1 transmit, and USB0VBUS analog VBUS sense/pulse pin for session request protocol.
47 PB2 bidirectional GPIO port B bit 2 (TTL); alternate functions I2C0SCL (open-drain, has active pull-up, so the port pin must not be configured as open drain) and T3CCP0 timer capture/compare/PWM 0.
48 PB3 bidirectional GPIO port B bit 3 (TTL); alternate functions I2C0SDA (open-drain data line) and T3CCP1 timer capture/compare/PWM 1.
49 PC3 bidirectional GPIO port C bit 3 (TTL); defaults to the JTAG/SWD function as TDO/SWO output, with alternate function T5CCP1 timer capture/compare/PWM 1.
50 PC2 bidirectional GPIO port C bit 2 (TTL); defaults to the JTAG TDI input after reset, with alternate function T5CCP0 timer capture/compare/PWM 0.
51 PC1 bidirectional GPIO port C bit 1 (TTL); defaults to the JTAG TMS/SWDIO function after reset, with alternate function T4CCP1 timer capture/compare/PWM 1.
52 PC0 bidirectional GPIO port C bit 0 (TTL); defaults to the JTAG/SWD clock (SWCLK/TCK) after reset, with alternate function T4CCP0 timer capture/compare/PWM 0.
53 PD6 bidirectional GPIO port D bit 6 (TTL); alternate functions M0FAULT0 PWM fault input, PhA0 QEI0 phase A, U2Rx UART2 receive, and WT5CCP0 wide timer capture/compare/PWM 0.
54 VDD power_in Positive supply for I/O and some logic.
55 GND power_in Ground reference for logic and I/O pins.
56 VDDC power_out Core supply of 1.2 V from the on-chip LDO; connect only to the other VDDC pins and the external capacitor specified in Table 24-12.
57 PB5 bidirectional GPIO port B bit 5 (TTL); alternate functions AIN11 analog input (not 5-V tolerant), CAN0Tx, M0PWM3 PWM output, SSI2Fss, and T1CCP1 timer capture/compare/PWM 1.
58 PB4 bidirectional GPIO port B bit 4 (TTL); alternate functions AIN10 analog input (not 5-V tolerant), CAN0Rx, M0PWM2 PWM output, SSI2Clk, and T1CCP0 timer capture/compare/PWM 0.
59 PE4 bidirectional GPIO port E bit 4 (TTL); alternate functions AIN9 analog input (not 5-V tolerant), CAN0Rx, I2C2SCL (open-drain, active pull-up), M0PWM4, M1PWM2, and U5Rx UART5 receive.
60 PE5 bidirectional GPIO port E bit 5 (TTL); alternate functions AIN8 analog input (not 5-V tolerant), CAN0Tx, I2C2SDA (open-drain data line), M0PWM5, M1PWM3, and U5Tx UART5 transmit.
61 PD0 bidirectional GPIO port D bit 0 (TTL); alternate functions AIN7 analog input (not 5-V tolerant), I2C3SCL (open-drain, active pull-up), M0PWM6, M1PWM0, SSI1Clk, SSI3Clk, and WT2CCP0 wide timer capture/compare/PWM 0.
62 PD1 bidirectional GPIO port D bit 1 (TTL); alternate functions AIN6 analog input (not 5-V tolerant), I2C3SDA (open-drain data line), M0PWM7, M1PWM1, SSI1Fss, SSI3Fss, and WT2CCP1 wide timer capture/compare/PWM 1.
63 PD2 bidirectional GPIO port D bit 2 (TTL); alternate functions AIN5 analog input (not 5-V tolerant), M0FAULT0 PWM fault input, SSI1Rx, SSI3Rx, USB0EPEN external power enable output, and WT3CCP0 wide timer capture/compare/PWM 0.
64 PD3 bidirectional GPIO port D bit 3 (TTL); alternate functions AIN4 analog input (not 5-V tolerant), IDX0 QEI0 index input, SSI1Tx, SSI3Tx, USB0PFLT external power-fault input in Host mode, and WT3CCP1 wide timer capture/compare/PWM 1.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: TM4C123GH6PMT7R
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: QFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: tm4c123gh6pmt7r-etched.step / tm4c123gh6pmt7r-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tm4c123gh6pmt7r.step / tm4c123gh6pmt7r.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (1411 pp, sha256 108350fb9d6cabfc, retrieved 2026-10-12, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF