# TM4C123GH6PMT7

**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

TM4C123GH6PMT7 from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PB6 | bidirectional | GPIO port B bit 6 (default GPIO), also muxed to M0PWM0, SSI2Rx, and T0CCP0; TTL-compatible levels. |
| 2 | VDDA | power_in | Positive supply for the analog circuits (ADC, analog comparators); must meet the recommended DC operating conditions in Table 24-5 regardless of system implementation. |
| 3 | GNDA | power_in | Ground reference for the analog circuits (ADC, analog comparators), separated from GND to limit digital noise coupling. |
| 4 | PB7 | bidirectional | GPIO port B bit 7 (default GPIO), also muxed to M0PWM1, SSI2Tx, and T0CCP1; TTL-compatible levels. |
| 5 | PF4 | bidirectional | GPIO port F bit 4 (default GPIO), also muxed to IDX0, M1FAULT0, T2CCP0, and USB0EPEN; TTL-compatible levels. |
| 6 | PE3 | bidirectional | GPIO port E bit 3 (default GPIO), also ADC analog input AIN0; AIN signals are not 5-V tolerant and pass through an isolation circuit. |
| 7 | PE2 | bidirectional | GPIO port E bit 2 (default GPIO), also ADC analog input AIN1; AIN signals are not 5-V tolerant and pass through an isolation circuit. |
| 8 | PE1 | bidirectional | GPIO port E bit 1 (default GPIO), also ADC analog input AIN2 and UART7 transmit U7Tx; AIN signals are not 5-V tolerant. |
| 9 | PE0 | bidirectional | GPIO port E bit 0 (default GPIO), also ADC analog input AIN3 and UART7 receive U7Rx; AIN signals are not 5-V tolerant. |
| 10 | PD7 | bidirectional | GPIO port D bit 7 (default GPIO), also NMI (non-maskable interrupt), PhB0, U2Tx, and WT5CCP1; protected by commit control and TTL-compatible. |
| 11 | VDD | power_in | Positive supply for I/O and some logic. |
| 12 | GND | power_in | Ground reference for logic and I/O pins. |
| 13 | PC7 | bidirectional | GPIO port C bit 7 (default GPIO), also analog comparator 0 negative input C0-, U3Tx, USB0PFLT, and WT1CCP1; C0- is 5-V tolerant. |
| 14 | PC6 | bidirectional | GPIO port C bit 6 (default GPIO), also analog comparator 0 positive input C0+, PhB1, U3Rx, USB0EPEN, and WT1CCP0; C0+ is 5-V tolerant. |
| 15 | PC5 | bidirectional | GPIO port C bit 5 (default GPIO), also analog comparator 1 positive input C1+, M0PWM7, PhA1, U1CTS, U1Tx, U4Tx, and WT0CCP1; C1+ is 5-V tolerant. |
| 16 | PC4 | bidirectional | GPIO port C bit 4 (default GPIO), also analog comparator 1 negative input C1-, IDX1, M0PWM6, U1RTS, U1Rx, U4Rx, and WT0CCP0; C1- is 5-V tolerant. |
| 17 | PA0 | bidirectional | GPIO port A bit 0 (default UART0 receive U0Rx), also CAN1Rx; TTL-compatible levels. |
| 18 | PA1 | bidirectional | GPIO port A bit 1 (default UART0 transmit U0Tx), also CAN1Tx; TTL-compatible levels. |
| 19 | PA2 | bidirectional | GPIO port A bit 2 (default SSI0 clock SSI0Clk); TTL-compatible levels. |
| 20 | PA3 | bidirectional | GPIO port A bit 3 (default SSI0 frame signal SSI0Fss); TTL-compatible levels. |
| 21 | PA4 | bidirectional | GPIO port A bit 4 (default SSI0 receive SSI0Rx); TTL-compatible levels. |
| 22 | PA5 | bidirectional | GPIO port A bit 5 (default SSI0 transmit SSI0Tx); TTL-compatible levels. |
| 23 | PA6 | bidirectional | GPIO port A bit 6, also I2C1 clock I2C1SCL (open-drain, has an active pull-up so the port pin must not be configured as open drain) and M1PWM2. |
| 24 | PA7 | bidirectional | GPIO port A bit 7, also I2C1 data I2C1SDA (open-drain, must be set open drain via GPIOODR) and M1PWM3. |
| 25 | VDDC | power_out | On-chip LDO output of 1.2 V supplying the processor core and most peripherals; connect only to the other VDDC pins and the external capacitor specified in Table 24-12. |
| 26 | VDD | power_in | Positive supply for I/O and some logic. |
| 27 | GND | power_in | Ground reference for logic and I/O pins. |
| 28 | PF0 | bidirectional | GPIO port F bit 0 (locked, default GPIO; requires unlock via GPIOLOCK and GPIOCR to reprogram), also NMI, analog comparator 0 output C0o, CAN0Rx, M1PWM4, PhA0, SSI1Rx, T0CCP0, and U1RTS. |
| 29 | PF1 | bidirectional | GPIO port F bit 1 (locked, default GPIO; requires unlock via GPIOLOCK and GPIOCR to reprogram), also analog comparator 1 output C1o, M1PWM5, PhB0, SSI1Tx, T0CCP1, TRD1, and U1CTS. |
| 30 | PF2 | bidirectional | GPIO port F bit 2, also M0FAULT0, M1PWM6, SSI1Clk, T1CCP0, and TRD0; TTL-compatible levels. |
| 31 | PF3 | bidirectional | GPIO port F bit 3, also CAN0Tx, M1PWM7, SSI1Fss, T1CCP1, and TRCLK; TTL-compatible levels. |
| 32 | WAKE | input | External input that brings the processor out of Hibernate mode when asserted; TTL-compatible levels. |
| 33 | HIB | output | Output that indicates the processor is in Hibernate mode; TTL-compatible levels. |
| 34 | XOSC0 | input | Hibernation module oscillator crystal input or external clock reference input, a 32.768-kHz crystal or oscillator for the Hibernation RTC; its amplitude should be less than VBAT. |
| 35 | GNDX | power_in | Ground for the Hibernation oscillator; connect to digital ground with the crystal load capacitors (crystal case) or directly to digital ground (external oscillator case). |
| 36 | XOSC1 | output | Hibernation module oscillator crystal output; leave unconnected when using a single-ended clock source. |
| 37 | VBAT | power_in | Power source for the Hibernation module, normally connected to the positive terminal of a battery as battery backup supply. |
| 38 | RST | input | System reset input with TTL-compatible levels. |
| 39 | GND | power_in | Ground reference for logic and I/O pins. |
| 40 | OSC0 | input | Main oscillator crystal input or external clock reference input. |
| 41 | OSC1 | output | Main oscillator crystal output; leave unconnected when using a single-ended clock source. |
| 42 | VDD | power_in | Positive supply for I/O and some logic. |
| 43 | PD4 | bidirectional | GPIO port D bit 4, also UART6 receive U6Rx, USB0DM (bidirectional differential data D-), and WT4CCP0; this pin is not 5-V tolerant. |
| 44 | PD5 | bidirectional | GPIO port D bit 5, also UART6 transmit U6Tx, USB0DP (bidirectional differential data D+), and WT4CCP1; this pin is not 5-V tolerant. |
| 45 | PB0 | bidirectional | GPIO port B bit 0, also T2CCP0, U1Rx, and USB0ID (senses the USB ID state, analog input); this pin is not 5-V tolerant. |
| 46 | PB1 | bidirectional | GPIO port B bit 1, also T2CCP1, U1Tx, and USB0VBUS (analog I/O used during session request protocol); this pin is not 5-V tolerant. |
| 47 | PB2 | bidirectional | GPIO port B bit 2, also I2C0 clock I2C0SCL (open-drain, has an active pull-up so the port pin must not be configured as open drain) and T3CCP0. |
| 48 | PB3 | bidirectional | GPIO port B bit 3, also I2C0 data I2C0SDA (open-drain, must be set open drain via GPIOODR) and T3CCP1. |
| 49 | PC3 | bidirectional | GPIO port C bit 3 (JTAG/SWD pin, default function TDO/SWO), also T5CCP1; commit-protected and TTL-compatible. |
| 50 | PC2 | bidirectional | GPIO port C bit 2 (JTAG/SWD pin, default function TDI, input with pull-up enabled after reset), also T5CCP0; commit-protected and TTL-compatible. |
| 51 | PC1 | bidirectional | GPIO port C bit 1 (JTAG/SWD pin, default function TMS/SWDIO), also T4CCP1; commit-protected and TTL-compatible. |
| 52 | PC0 | bidirectional | GPIO port C bit 0 (JTAG/SWD pin, default function TCK/SWCLK), also T4CCP0; commit-protected and TTL-compatible. |
| 53 | PD6 | bidirectional | GPIO port D bit 6, also M0FAULT0, PhA0, U2Rx, and WT5CCP0; TTL-compatible levels. |
| 54 | VDD | power_in | Positive supply for I/O and some logic. |
| 55 | GND | power_in | Ground reference for logic and I/O pins. |
| 56 | VDDC | power_out | On-chip LDO output of 1.2 V supplying the processor core and most peripherals; connect only to the other VDDC pins and the external capacitor specified in Table 24-12. |
| 57 | PB5 | bidirectional | GPIO port B bit 5, also ADC analog input AIN11, CAN0Tx, M0PWM3, SSI2Fss, and T1CCP1; AIN signals are not 5-V tolerant. |
| 58 | PB4 | bidirectional | GPIO port B bit 4, also ADC analog input AIN10, CAN0Rx, M0PWM2, SSI2Clk, and T1CCP0; AIN signals are not 5-V tolerant. |
| 59 | PE4 | bidirectional | GPIO port E bit 4, also ADC analog input AIN9, CAN0Rx, I2C2SCL (open-drain, active pull-up so must not be configured as open drain), M0PWM4, M1PWM2, and U5Rx; AIN signals are not 5-V tolerant. |
| 60 | PE5 | bidirectional | GPIO port E bit 5, also ADC analog input AIN8, CAN0Tx, I2C2SDA (open-drain, must be set open drain via GPIOODR), M0PWM5, M1PWM3, and U5Tx; AIN signals are not 5-V tolerant. |
| 61 | PD0 | bidirectional | GPIO port D bit 0, also ADC analog input AIN7, I2C3SCL (open-drain, active pull-up so must not be configured as open drain), M0PWM6, M1PWM0, SSI1Clk, SSI3Clk, and WT2CCP0; AIN signals are not 5-V tolerant. |
| 62 | PD1 | bidirectional | GPIO port D bit 1, also ADC analog input AIN6, I2C3SDA (open-drain, must be set open drain via GPIOODR), M0PWM7, M1PWM1, SSI1Fss, SSI3Fss, and WT2CCP1; AIN signals are not 5-V tolerant. |
| 63 | PD2 | bidirectional | GPIO port D bit 2, also ADC analog input AIN5, M0FAULT0, SSI1Rx, SSI3Rx, USB0EPEN, and WT3CCP0; AIN signals are not 5-V tolerant. |
| 64 | PD3 | bidirectional | GPIO port D bit 3, also ADC analog input AIN4, IDX0, SSI1Tx, SSI3Tx, USB0PFLT, and WT3CCP1; AIN signals are not 5-V tolerant. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |

## CAD (KiCad official)

- Symbol: `TM4C123GH6PMT7`
- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`
- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `tm4c123gh6pmt7-etched.step` / `tm4c123gh6pmt7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tm4c123gh6pmt7.step` / `tm4c123gh6pmt7.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tm4c123gh6pm) (1411 pp, sha256 `108350fb9d6cabfc`, retrieved 2026-10-10, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tm4c123gh6pmt7-datasheet.pdf)