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TM4C123FE6PMIR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TM4C123FE6PMIR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

TM4C123FE6PMIR from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PB6 bidirectional GPIO port B bit 6 (TTL); alternate functions include I2C5SCL (has an active pull-up, so the pin should not be set open-drain), M0PWM0, SSI2Rx and T0CCP0.
2 VDDA power_in Positive supply for the analog circuits (ADC, analog comparators); it must be supplied within the Table 23-5 specification regardless of system implementation.
3 GNDA power_in Ground reference for the analog circuits (ADC, analog comparators), separated from GND to limit digital noise on the analog functions.
4 PB7 bidirectional GPIO port B bit 7 (TTL); alternate functions include I2C5SDA (open-drain), M0PWM1, SSI2Tx and T0CCP1.
5 PF4 bidirectional GPIO port F bit 4 (TTL); alternate functions include QEI0 index IDX0, M0FAULT2, M1FAULT0, T2CCP0 and USB0EPEN (host-mode VBUS power-enable output).
6 PE3 bidirectional GPIO port E bit 3; serves as ADC input AIN0, which is not 5-V tolerant and passes through an isolation circuit.
7 PE2 bidirectional GPIO port E bit 2; serves as ADC input AIN1, which is not 5-V tolerant and passes through an isolation circuit.
8 PE1 bidirectional GPIO port E bit 1 (TTL); serves as ADC input AIN2 (not 5-V tolerant) and alternate function U7Tx (UART7 transmit).
9 PE0 bidirectional GPIO port E bit 0 (TTL); serves as ADC input AIN3 (not 5-V tolerant) and alternate function U7Rx (UART7 receive).
10 PD7 bidirectional GPIO port D bit 7 (TTL); alternate functions include NMI (non-maskable interrupt), M0FAULT1, PhB0, U2Tx and WT5CCP1, and the pin is commit-protected so it must be unlocked before reprogramming.
11 VDD power_in Positive supply for I/O and some logic.
12 GND power_in Ground reference for logic and I/O pins.
13 PC7 bidirectional GPIO port C bit 7 (TTL); analog comparator 0 negative input C0- (5-V tolerant), with alternate functions U3Tx, USB0PFLT and WT1CCP1.
14 PC6 bidirectional GPIO port C bit 6 (TTL); analog comparator 0 positive input C0+ (5-V tolerant), with alternate functions U3Rx, PhB1, USB0EPEN and WT1CCP0.
15 PC5 bidirectional GPIO port C bit 5 (TTL); analog comparator 1 positive input C1+ (5-V tolerant), with alternate functions M0PWM7, PhA1, U1CTS, U1Tx, U4Tx and WT0CCP1.
16 PC4 bidirectional GPIO port C bit 4 (TTL); analog comparator 1 negative input C1- (5-V tolerant), with alternate functions IDX1, M0PWM6, U1RTS, U1Rx, U4Rx and WT0CCP0.
17 PA0 bidirectional GPIO port A bit 0 (TTL); default function is UART0 receive U0Rx, with alternate function CAN1Rx.
18 PA1 bidirectional GPIO port A bit 1 (TTL); default function is UART0 transmit U0Tx, with alternate function CAN1Tx.
19 PA2 bidirectional GPIO port A bit 2 (TTL); default function is SSI0 clock SSI0Clk.
20 PA3 bidirectional GPIO port A bit 3 (TTL); default function is SSI0 frame signal SSI0Fss.
21 PA4 bidirectional GPIO port A bit 4 (TTL); default function is SSI0 receive SSI0Rx.
22 PA5 bidirectional GPIO port A bit 5 (TTL); default function is SSI0 transmit SSI0Tx.
23 PA6 bidirectional GPIO port A bit 6; alternate functions include I2C1SCL (has an active pull-up, so the pin should not be configured open-drain) and M1PWM2.
24 PA7 bidirectional GPIO port A bit 7; alternate functions include I2C1SDA (open-drain, set via GPIOODR) and M1PWM3.
25 VDDC power_in Core logic supply at 1.2 V from the on-chip LDO; VDDC pins should only be connected to each other and to the external capacitor specified in Table 23-12.
26 VDD power_in Positive supply for I/O and some logic.
27 GND power_in Ground reference for logic and I/O pins.
28 PF0 bidirectional GPIO port F bit 0 (locked by default and commit-protected); alternate functions include NMI, C0o (analog comparator 0 output), CAN0Rx, M1PWM4, PhA0, SSI1Rx, T0CCP0 and U1RTS.
29 PF1 bidirectional GPIO port F bit 1 (TTL); analog comparator 1 output C1o, with alternate functions M1PWM5, PhB0, SSI1Tx, T0CCP1, TRD1 and U1CTS.
30 PF2 bidirectional GPIO port F bit 2 (TTL); alternate functions include M0FAULT0, M1PWM6, SSI1Clk, T1CCP0 and TRD0.
31 PF3 bidirectional GPIO port F bit 3 (TTL); alternate functions include CAN0Tx, M0FAULT1, M1PWM7, SSI1Fss, T1CCP1 and TRCLK.
32 PG5 bidirectional GPIO port G bit 5; alternate functions include I2C1SDA (open-drain), IDX1, M0PWM5, M1PWM3, U2Tx, USB0PFLT and WT0CCP1.
33 PG4 bidirectional GPIO port G bit 4; alternate functions include I2C1SCL (has an active pull-up, so the pin should not be configured open-drain), M0PWM4, M1PWM2, PhB1, U2Rx, USB0EPEN and WT0CCP0.
34 PG3 bidirectional GPIO port G bit 3; alternate functions include I2C4SDA (open-drain), M0FAULT2, M1PWM1, PhA1 and T5CCP1.
35 PG2 bidirectional GPIO port G bit 2; alternate functions include I2C4SCL (has an active pull-up), M0FAULT1, M1PWM0 and T5CCP0.
36 PG1 bidirectional GPIO port G bit 1; alternate functions include I2C3SDA (open-drain), M1FAULT2, PhB1 and T4CCP1.
37 PG0 bidirectional GPIO port G bit 0; alternate functions include I2C3SCL (has an active pull-up), M1FAULT1, PhA1 and T4CCP0.
38 RST input TTL-compatible system reset input; asserting it resets the core and on-chip peripherals.
39 GND power_in Ground reference for logic and I/O pins.
40 OSC0 input Main oscillator crystal input or external clock reference input (analog).
41 OSC1 output Main oscillator crystal output; leave unconnected when using a single-ended clock source.
42 VDD power_in Positive supply for I/O and some logic.
43 PD4 bidirectional GPIO port D bit 4, not 5-V tolerant; USB0DM is the bidirectional differential data pin (D-) for USB0, with alternate functions U6Rx and WT4CCP0.
44 PD5 bidirectional GPIO port D bit 5, not 5-V tolerant; USB0DP is the bidirectional differential data pin (D+) for USB0, with alternate functions U6Tx and WT4CCP1.
45 PB0 bidirectional GPIO port B bit 0, not 5-V tolerant; USB0ID senses the USB ID state (analog), with alternate functions T2CCP0 and U1Rx.
46 PB1 bidirectional GPIO port B bit 1, not 5-V tolerant; USB0VBUS is an analog pin used during session request protocol to sense and pulse VBUS, with alternate functions T2CCP1 and U1Tx.
47 PB2 bidirectional GPIO port B bit 2; I2C0SCL (has an active pull-up, so the pin should not be configured open-drain) with alternate function T3CCP0.
48 PB3 bidirectional GPIO port B bit 3; I2C0SDA (open-drain) with alternate function T3CCP1.
49 PC3 bidirectional GPIO port C bit 3 (JTAG/SWD function after reset); carries the SWO/TDO output, with alternate function T5CCP1.
50 PC2 bidirectional GPIO port C bit 2 (JTAG function after reset); carries the JTAG TDI input, with alternate function T5CCP0.
51 PC1 bidirectional GPIO port C bit 1 (JTAG/SWD function after reset); carries the TMS/SWDIO signal, with alternate function T4CCP1.
52 PC0 bidirectional GPIO port C bit 0 (JTAG/SWD function after reset); carries the SWCLK/TCK clock input, with alternate function T4CCP0.
53 PD6 bidirectional GPIO port D bit 6 (TTL); alternate functions include M0FAULT0, PhA0, U2Rx and WT5CCP0.
54 VDD power_in Positive supply for I/O and some logic.
55 GND power_in Ground reference for logic and I/O pins.
56 VDDC power_in Core logic supply at 1.2 V from the on-chip LDO; VDDC pins should only be connected to each other and to the external capacitor specified in Table 23-12.
57 PB5 bidirectional GPIO port B bit 5 (TTL); ADC input AIN11 (not 5-V tolerant), with alternate functions CAN0Tx, M0PWM3, SSI2Fss and T1CCP1.
58 PB4 bidirectional GPIO port B bit 4 (TTL); ADC input AIN10 (not 5-V tolerant), with alternate functions CAN0Rx, M0PWM2, SSI2Clk and T1CCP0.
59 PE4 bidirectional GPIO port E bit 4 (TTL); ADC input AIN9 (not 5-V tolerant), with alternate functions CAN0Rx, I2C2SCL (active pull-up), M0PWM4, M1PWM2 and U5Rx.
60 PE5 bidirectional GPIO port E bit 5 (TTL); ADC input AIN8 (not 5-V tolerant), with alternate functions CAN0Tx, I2C2SDA (open-drain), M0PWM5, M1PWM3 and U5Tx.
61 PD0 bidirectional GPIO port D bit 0 (TTL); ADC input AIN7 (not 5-V tolerant), with alternate functions I2C3SCL, M0PWM6, M1PWM0, SSI1Clk, SSI3Clk and WT2CCP0.
62 PD1 bidirectional GPIO port D bit 1 (TTL); ADC input AIN6 (not 5-V tolerant), with alternate functions I2C3SDA (open-drain), M0PWM7, M1PWM1, SSI1Fss, SSI3Fss and WT2CCP1.
63 PD2 bidirectional GPIO port D bit 2 (TTL); ADC input AIN5 (not 5-V tolerant), with alternate functions M0FAULT0, SSI1Rx, SSI3Rx, USB0EPEN and WT3CCP0.
64 PD3 bidirectional GPIO port D bit 3 (TTL); ADC input AIN4 (not 5-V tolerant), with alternate functions IDX0, SSI1Tx, SSI3Tx, USB0PFLT and WT3CCP1.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: TM4C123FE6PMIR
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: tm4c123fe6pmir-etched.step / tm4c123fe6pmir-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tm4c123fe6pmir.step / tm4c123fe6pmir.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (1372 pp, sha256 484c617cb71acff2, retrieved 2026-10-12, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF