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TM4C1230D5PMIR

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Texas Instruments Pre-ordered Chips, LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterface icstm4c1230d5pmirfactory-2.0.0extractor-text

Verified TM4C1230D5PMIR

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 64 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TM4C1230D5PMIR · LQFP-64(10x10) · 64 pins
  • ✓copper: 64 copper pads, none touching another net
  • ✓datasheet: all 64 pin names found in the 1107-page datasheet
  • ✓distributor: lcsc C544881, digikey 296-TM4C1230D5PMIRTR-ND, mouser 595-TM4C1230D5PMIR
  • ✓family: LQFP-64_10x10mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-okaijj_k/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 64 pins = 64 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 64 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tm4c1230d5pmir.kicad_sym✓ tm4c1230d5pmir.kicad_mod✓ tm4c1230d5pmir.step
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TM4C1230D5PMIR

Texas Instruments · Pre-ordered Chips · LQFP-64(10x10)

TM4C1230D5PMIR from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PB6 bidirectional GPIO port B bit 6, TTL-compatible, with alternate functions I2C5SCL (open-drain, active pull-up), SSI2Rx and T0CCP0.
2 VDDA power_in Positive supply for the analog circuits (ADC, analog comparators); must meet the voltage specification in Table 20-5 regardless of system implementation.
3 GNDA power_in Ground reference for the analog circuits (ADC, analog comparators), separated from GND to reduce noise coupling.
4 PB7 bidirectional GPIO port B bit 7, TTL-compatible, with alternate functions I2C5SDA (open-drain), SSI2Tx and T0CCP1.
5 PF4 bidirectional GPIO port F bit 4, TTL-compatible, with alternate function T2CCP0 (16/32-bit timer 2 capture/compare/PWM 0).
6 PE3 bidirectional GPIO port E bit 3, with analog alternate function AIN0 (ADC input 0); configure DEN=0 and AMSEL=1 for analog use.
7 PE2 bidirectional GPIO port E bit 2, with analog alternate function AIN1 (ADC input 1); configure DEN=0 and AMSEL=1 for analog use.
8 PE1 bidirectional GPIO port E bit 1, with analog alternate function AIN2 (ADC input 2) and UART7 transmit U7Tx.
9 PE0 bidirectional GPIO port E bit 0, with analog alternate function AIN3 (ADC input 3) and UART7 receive U7Rx.
10 PD7 bidirectional GPIO port D bit 7, TTL-compatible, with alternate functions NMI (non-maskable interrupt), U2Tx and WT5CCP1; locked by commit control.
11 VDD power_in Positive supply for I/O and some logic; voltage limits are given in Table 20-5.
12 GND power_in Ground reference for logic and I/O pins.
13 PC7 bidirectional GPIO port C bit 7, TTL-compatible, with alternate functions C0- (analog comparator 0 negative input), U3Tx and WT1CCP1.
14 PC6 bidirectional GPIO port C bit 6, TTL-compatible, with alternate functions C0+ (analog comparator 0 positive input), U3Rx and WT1CCP0.
15 PC5 bidirectional GPIO port C bit 5, TTL-compatible, with alternate functions C1+ (analog comparator 1 positive input), U1CTS, U1Tx, U4Tx and WT0CCP1.
16 PC4 bidirectional GPIO port C bit 4, TTL-compatible, with alternate functions C1- (analog comparator 1 negative input), U1RTS, U1Rx, U4Rx and WT0CCP0.
17 PA0 bidirectional GPIO port A bit 0, TTL-compatible, with alternate function U0Rx (UART0 receive), default UART function at reset.
18 PA1 bidirectional GPIO port A bit 1, TTL-compatible, with alternate function U0Tx (UART0 transmit), default UART function at reset.
19 PA2 bidirectional GPIO port A bit 2, TTL-compatible, with alternate function SSI0Clk (SSI module 0 clock), default SSI function at reset.
20 PA3 bidirectional GPIO port A bit 3, TTL-compatible, with alternate function SSI0Fss (SSI module 0 frame signal), default SSI function at reset.
21 PA4 bidirectional GPIO port A bit 4, TTL-compatible, with alternate function SSI0Rx (SSI module 0 receive), default SSI function at reset.
22 PA5 bidirectional GPIO port A bit 5, TTL-compatible, with alternate function SSI0Tx (SSI module 0 transmit), default SSI function at reset.
23 PA6 bidirectional GPIO port A bit 6, with alternate function I2C1SCL (open-drain, active pull-up on the clock signal).
24 PA7 bidirectional GPIO port A bit 7, with alternate function I2C1SDA (open-drain data).
25 VDDC power_out Output of the on-chip LDO supplying the 1.2 V core logic; connect only to the other VDDC pins and the external capacitor specified in Table 20-12.
26 VDD power_in Positive supply for I/O and some logic; voltage limits are given in Table 20-5.
27 GND power_in Ground reference for logic and I/O pins.
28 PF0 bidirectional GPIO port F bit 0, TTL-compatible, with alternate functions C0o, CAN0Rx, NMI, SSI1Rx, T0CCP0 and U1RTS; locked by commit control.
29 PF1 bidirectional GPIO port F bit 1, TTL-compatible, with alternate functions C1o, SSI1Tx, T0CCP1, TRD1 and U1CTS.
30 PF2 bidirectional GPIO port F bit 2, TTL-compatible, with alternate functions SSI1Clk, T1CCP0 and TRD0.
31 PF3 bidirectional GPIO port F bit 3, TTL-compatible, with alternate functions CAN0Tx, SSI1Fss, T1CCP1 and TRCLK.
32 PG5 bidirectional GPIO port G bit 5, TTL-compatible, with alternate functions I2C1SDA (open-drain), U2Tx and WT0CCP1.
33 PG4 bidirectional GPIO port G bit 4, TTL-compatible, with alternate functions I2C1SCL (open-drain, active pull-up), U2Rx and WT0CCP0.
34 PG3 bidirectional GPIO port G bit 3, TTL-compatible, with alternate functions I2C4SDA (open-drain) and T5CCP1.
35 PG2 bidirectional GPIO port G bit 2, TTL-compatible, with alternate functions I2C4SCL (open-drain, active pull-up) and T5CCP0.
36 PG1 bidirectional GPIO port G bit 1, TTL-compatible, with alternate functions I2C3SDA (open-drain) and T4CCP1.
37 PG0 bidirectional GPIO port G bit 0, TTL-compatible, with alternate functions I2C3SCL (open-drain, active pull-up) and T4CCP0.
38 RST input System reset input, TTL-compatible; asserting it resets the device.
39 GND power_in Ground reference for logic and I/O pins.
40 OSC0 input Main oscillator crystal input or an external clock reference input (analog).
41 OSC1 output Main oscillator crystal output; leave unconnected when using a single-ended clock source.
42 VDD power_in Positive supply for I/O and some logic; voltage limits are given in Table 20-5.
43 PD4 bidirectional GPIO port D bit 4, TTL-compatible but not 5-V tolerant, with alternate functions U6Rx and WT4CCP0.
44 PD5 bidirectional GPIO port D bit 5, TTL-compatible but not 5-V tolerant, with alternate functions U6Tx and WT4CCP1.
45 PB0 bidirectional GPIO port B bit 0, TTL-compatible but not 5-V tolerant, with alternate functions T2CCP0 and U1Rx.
46 PB1 bidirectional GPIO port B bit 1, TTL-compatible but not 5-V tolerant, with alternate functions T2CCP1 and U1Tx.
47 PB2 bidirectional GPIO port B bit 2, with alternate functions I2C0SCL (open-drain, active pull-up) and T3CCP0.
48 PB3 bidirectional GPIO port B bit 3, with alternate functions I2C0SDA (open-drain) and T3CCP1.
49 PC3 bidirectional GPIO port C bit 3, TTL-compatible, with alternate functions SWO/TDO (JTAG trace output), and T5CCP1.
50 PC2 bidirectional GPIO port C bit 2, TTL-compatible, with alternate functions TDI (JTAG test data input) and T5CCP0.
51 PC1 bidirectional GPIO port C bit 1, TTL-compatible, with alternate functions SWDIO/TMS (JTAG/SWD mode select) and T4CCP1.
52 PC0 bidirectional GPIO port C bit 0, TTL-compatible, with alternate functions SWCLK/TCK (JTAG/SWD clock) and T4CCP0.
53 PD6 bidirectional GPIO port D bit 6, TTL-compatible, with alternate functions U2Rx and WT5CCP0.
54 VDD power_in Positive supply for I/O and some logic; voltage limits are given in Table 20-5.
55 GND power_in Ground reference for logic and I/O pins.
56 VDDC power_out Output of the on-chip LDO supplying the 1.2 V core logic; connect only to the other VDDC pins and the external capacitor specified in Table 20-12.
57 PB5 bidirectional GPIO port B bit 5, with analog alternate function AIN11 and alternate functions CAN0Tx, SSI2Fss and T1CCP1.
58 PB4 bidirectional GPIO port B bit 4, with analog alternate function AIN10 and alternate functions CAN0Rx, SSI2Clk and T1CCP0.
59 PE4 bidirectional GPIO port E bit 4, with analog alternate function AIN9 and alternate functions CAN0Rx, I2C2SCL (open-drain) and U5Rx.
60 PE5 bidirectional GPIO port E bit 5, with analog alternate function AIN8 and alternate functions CAN0Tx, I2C2SDA (open-drain) and U5Tx.
61 PD0 bidirectional GPIO port D bit 0, with analog alternate function AIN7 and alternate functions I2C3SCL (open-drain), SSI1Clk, SSI3Clk and WT2CCP0.
62 PD1 bidirectional GPIO port D bit 1, with analog alternate function AIN6 and alternate functions I2C3SDA (open-drain), SSI1Fss, SSI3Fss and WT2CCP1.
63 PD2 bidirectional GPIO port D bit 2, with analog alternate function AIN5 and alternate functions SSI1Rx, SSI3Rx and WT3CCP0.
64 PD3 bidirectional GPIO port D bit 3, with analog alternate function AIN4 and alternate functions SSI1Tx, SSI3Tx and WT3CCP1.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-64(10x10)
Category Interface ICs
Pins 64

CAD (KiCad official)

  • Symbol: TM4C1230D5PMIR
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: tm4c1230d5pmir-etched.step / tm4c1230d5pmir-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tm4c1230d5pmir.step / tm4c1230d5pmir.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (1107 pp, sha256 cf04f83060650d46, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF