component
TM4886
Public Made by Adomby adom
Tritech MOS MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TM4886
Tritech MOS · MOSFETs · SOP-8
TM4886 from Tritech MOS, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of MOSFET 1 (N-channel); pin 1 marked on package; VDS rated 100V. |
| 2 | G1 | input | Gate of MOSFET 1; gate-source voltage limit ±20V, threshold 1.0 to 2.5V. |
| 3 | S2 | passive | Source of MOSFET 2 (N-channel); VDS rated 100V. |
| 4 | G2 | input | Gate of MOSFET 2; gate-source voltage limit ±20V, threshold 1.0 to 2.5V. |
| 5 | D2 | passive | Drain of MOSFET 2, tied to pin 6; 100V drain-source rating, 8A continuous at TC=25°C. |
| 6 | D2 | passive | Drain of MOSFET 2, tied to pin 5; 100V drain-source rating, 8A continuous at TC=25°C. |
| 7 | D1 | passive | Drain of MOSFET 1, tied to pin 8; 100V drain-source rating, 8A continuous at TC=25°C. |
| 8 | D1 | passive | Drain of MOSFET 1, tied to pin 7; 100V drain-source rating, 8A continuous at TC=25°C. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Tritech MOS |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDS | 100 | V | 1 | |||
| Gate-Source Voltage | VGS | -20 | 20 | V | 1 | ||
| Continuous Drain Current | ID | 8 | A | ID@TC=25℃, VGS @ 10V | 1 | ||
| Continuous Drain Current | ID | 5 | A | ID@TC=100℃, VGS @ 10V | 1 | ||
| Pulsed Drain Current | IDM | 15 | A | 1 | |||
| Single Pulse Avalanche Energy | EAS | 6.1 | mJ | EAS condition: TJ=25℃, VDD=50V, VG=10V, L=0.5mH, Rg=25Ω, IAS=4A | 1 | ||
| Total Power Dissipation | PD | 5 | W | TA=25℃ | 1 | ||
| Storage Temperature Range | TSTG | -55 | 150 | ℃ | 1 | ||
| Operating Junction Temperature Range | TJ | -55 | 150 | ℃ | 1 | ||
| Thermal Resistance Junction-ambient | RθJA | 125 | ℃/W | 1 | |||
| Thermal Resistance Junction-Case | RθJC | 3.6 | ℃/W | 1 | |||
| Drain-Source Breakdown Voltage | V(BR)DSS | 100 | V | VGS=0V, ID=250μA | 2 | ||
| Zero Gate Voltage Drain Current | IDSS | 1 | μA | VDS=100V, VGS=0V, | 2 | ||
| Gate to Body Leakage Current | IGSS | -100 | 100 | nA | VDS=0V, VGS=±20V | 2 | |
| Gate Threshold Voltage | VGS(th) | 1 | 1.5 | 2.5 | V | VDS=VGS, ID=250μA | 2 |
| Static Drain-Source on-Resistance | RDS(on) | 88 | 105 | mΩ | VGS=10V, ID=3A | 2 | |
| Static Drain-Source on-Resistance | RDS(on) | 100 | 128 | mΩ | VGS=4.5V, ID=2A | 2 | |
| Maximum Continuous Drain to Source Diode Forward Current | IS | 3 | A | 2 | |||
| Maximum Pulsed Drain to Source Diode Forward Current | ISM | 8 | A | 2 | |||
| Drain to Source Diode Forward Voltage | VSD | 1.2 | V | VGS=0V, IS=3A | 2 |
CAD (KiCad official)
- Symbol:
TM4886 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
tm4886-etched.step/tm4886-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tm4886.step/tm4886.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Tritech MOS datasheet (5 pp, sha256
6ef94400309d37e9, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TM4886
**Tritech MOS** · MOSFETs · SOP-8
TM4886 from Tritech MOS, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of MOSFET 1 (N-channel); pin 1 marked on package; VDS rated 100V. |
| 2 | G1 | input | Gate of MOSFET 1; gate-source voltage limit ±20V, threshold 1.0 to 2.5V. |
| 3 | S2 | passive | Source of MOSFET 2 (N-channel); VDS rated 100V. |
| 4 | G2 | input | Gate of MOSFET 2; gate-source voltage limit ±20V, threshold 1.0 to 2.5V. |
| 5 | D2 | passive | Drain of MOSFET 2, tied to pin 6; 100V drain-source rating, 8A continuous at TC=25°C. |
| 6 | D2 | passive | Drain of MOSFET 2, tied to pin 5; 100V drain-source rating, 8A continuous at TC=25°C. |
| 7 | D1 | passive | Drain of MOSFET 1, tied to pin 8; 100V drain-source rating, 8A continuous at TC=25°C. |
| 8 | D1 | passive | Drain of MOSFET 1, tied to pin 7; 100V drain-source rating, 8A continuous at TC=25°C. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Tritech MOS |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDS | | | 100 | V | | 1 |
| Gate-Source Voltage | VGS | -20 | | 20 | V | | 1 |
| Continuous Drain Current | ID | | | 8 | A | ID@TC=25℃, VGS @ 10V | 1 |
| Continuous Drain Current | ID | | | 5 | A | ID@TC=100℃, VGS @ 10V | 1 |
| Pulsed Drain Current | IDM | | | 15 | A | | 1 |
| Single Pulse Avalanche Energy | EAS | | | 6.1 | mJ | EAS condition: TJ=25℃, VDD=50V, VG=10V, L=0.5mH, Rg=25Ω, IAS=4A | 1 |
| Total Power Dissipation | PD | | | 5 | W | TA=25℃ | 1 |
| Storage Temperature Range | TSTG | -55 | | 150 | ℃ | | 1 |
| Operating Junction Temperature Range | TJ | -55 | | 150 | ℃ | | 1 |
| Thermal Resistance Junction-ambient | RθJA | | | 125 | ℃/W | | 1 |
| Thermal Resistance Junction-Case | RθJC | | | 3.6 | ℃/W | | 1 |
| Drain-Source Breakdown Voltage | V(BR)DSS | 100 | | | V | VGS=0V, ID=250μA | 2 |
| Zero Gate Voltage Drain Current | IDSS | | | 1 | μA | VDS=100V, VGS=0V, | 2 |
| Gate to Body Leakage Current | IGSS | -100 | | 100 | nA | VDS=0V, VGS=±20V | 2 |
| Gate Threshold Voltage | VGS(th) | 1 | 1.5 | 2.5 | V | VDS=VGS, ID=250μA | 2 |
| Static Drain-Source on-Resistance | RDS(on) | | 88 | 105 | mΩ | VGS=10V, ID=3A | 2 |
| Static Drain-Source on-Resistance | RDS(on) | | 100 | 128 | mΩ | VGS=4.5V, ID=2A | 2 |
| Maximum Continuous Drain to Source Diode Forward Current | IS | | | 3 | A | | 2 |
| Maximum Pulsed Drain to Source Diode Forward Current | ISM | | | 8 | A | | 2 |
| Drain to Source Diode Forward Voltage | VSD | | | 1.2 | V | VGS=0V, IS=3A | 2 |
## CAD (KiCad official)
- Symbol: `TM4886`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `tm4886-etched.step` / `tm4886-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tm4886.step` / `tm4886.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Tritech MOS datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603002842907635712) (5 pp, sha256 `6ef94400309d37e9`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tm4886-datasheet.pdf)