component
TM4559AS
Public Made by Adomby adom
Tritech MOS MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownTM4559AS
Tritech MOS · MOSFETs · SOP-8
TM4559AS from Tritech MOS, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of MOSFET 1 (N-channel per the schematic, VDS = 60V, ID = 6A). |
| 2 | G1 | input | Gate of MOSFET 1 (N-channel), with a gate-source voltage limit of ±20V. |
| 3 | S2 | passive | Source of MOSFET 2 (P-channel per the schematic, VDS = -60V, ID = -5A). |
| 4 | G2 | input | Gate of MOSFET 2 (P-channel), with a gate-source voltage limit of ±20V. |
| 5 | D2 | passive | Drain of MOSFET 2 (P-channel), rated VDS = -60V, tied to pin 6. |
| 6 | D2 | passive | Drain of MOSFET 2 (P-channel), rated VDS = -60V, tied to pin 5. |
| 7 | D1 | passive | Drain of MOSFET 1 (N-channel), rated VDS = 60V, tied to pin 8. |
| 8 | D1 | passive | Drain of MOSFET 1 (N-channel), rated VDS = 60V, tied to pin 7. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Tritech MOS |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage, N-Channel | VDS | 60 | V | 1 | |||
| Drain-Source Voltage, P-Channel | VDS | -60 | V | 1 | |||
| Gate-Source Voltage, N-Channel | VGS | 20 | V | 1 | |||
| Gate-Source Voltage, P-Channel | VGS | 20 | V | 1 | |||
| Continuous Drain Current, N-Channel | ID | 6 | A | VGS @ 10V, TA=25℃ | 1 | ||
| Continuous Drain Current, P-Channel | ID | -5 | A | VGS @ 10V, TA=25℃ | 1 | ||
| Continuous Drain Current, N-Channel | ID | 4 | A | VGS @ 10V, TA=70℃ | 1 | ||
| Continuous Drain Current, P-Channel | ID | -3.5 | A | VGS @ 10V, TA=70℃ | 1 | ||
| Pulsed Drain Current, N-Channel | IDM | 11 | A | 1 | |||
| Pulsed Drain Current, P-Channel | IDM | -8.5 | A | 1 | |||
| Single Pulse Avalanche Energy, N-Channel | EAS | 22.5 | mJ | 1 | |||
| Single Pulse Avalanche Energy, P-Channel | EAS | 35.3 | mJ | 1 | |||
| Avalanche Current, N-Channel | IAS | 22.6 | A | 1 | |||
| Avalanche Current, P-Channel | IAS | -26.6 | A | 1 | |||
| Total Power Dissipation, N-Channel | PD | 2.5 | W | TA=25℃ | 1 | ||
| Total Power Dissipation, P-Channel | PD | 2.5 | W | TA=25℃ | 1 | ||
| Storage Temperature Range | TSTG | -55 | 150 | ℃ | 1 | ||
| Operating Junction Temperature Range | TJ | -55 | 150 | ℃ | 1 | ||
| Thermal Resistance Junction-Ambient | RθJA | 85 | ℃/W | 1 | |||
| Drain-Source Breakdown Voltage, N-Channel | V(BR)DSS | 60 | V | VGS=0V, ID=250μA | 2 | ||
| Zero Gate Voltage Drain Current, N-Channel | IDSS | 1 | μA | VDS=60V, VGS = 0V | 2 | ||
| Gate to Body Leakage Current, N-Channel | IGSS | -100 | 100 | nA | VDS=0V, VGS = ±20V | 2 | |
| Gate Threshold Voltage, N-Channel | VGS(th) | 1 | 1.6 | 2.5 | V | VDS=VGS, ID=250μA | 2 |
| Static Drain-Source on-Resistance, N-Channel | RDS(on) | 30 | 40 | mΩ | VGS=10V, ID=5A | 2 | |
| Static Drain-Source on-Resistance, N-Channel | RDS(on) | 36 | 50 | mΩ | VGS=4.5V, ID=3A | 2 | |
| Maximum Continuous Drain to Source Diode Forward Current, N-Channel | IS | 6 | A | 2 | |||
| Maximum Pulsed Drain to Source Diode Forward Current, N-Channel | ISM | 20 | A | 2 | |||
| Drain to Source Diode Forward Voltage, N-Channel | VSD | 1.2 | V | VGS=0V, IS=5A | 2 | ||
| Drain-Source Breakdown Voltage, P-Channel | BVDSS | -60 | V | VGS=0V, ID=-250uA | 3 | ||
| Static Drain-Source On-Resistance, P-Channel | RDS(ON) | 70 | 90 | mΩ | VGS=-10V, ID=-3.5A | 3 | |
| Static Drain-Source On-Resistance, P-Channel | RDS(ON) | 90 | 105 | mΩ | VGS=-4.5V, ID=-3.1A | 3 | |
| Gate Threshold Voltage, P-Channel | VGS(th) | -1 | -2.5 | V | VGS=VDS, ID=-250uA | 3 | |
| Drain-Source Leakage Current, P-Channel | IDSS | 1 | uA | VDS=-48V, VGS=0V, TJ=25℃ | 3 | ||
| Drain-Source Leakage Current, P-Channel | IDSS | 5 | uA | VDS=-48V, VGS=0V, TJ=55℃ | 3 | ||
| Gate-Source Leakage Current, P-Channel | IGSS | -100 | 100 | nA | VGS=±20V, VDS=0V | 3 | |
| Continuous Source Current, P-Channel | IS | -6 | A | VG=VD=0V, Force Current | 3 | ||
| Diode Forward Voltage, P-Channel | VSD | -1.2 | V | VGS=0V, IS=-1A, TJ=25℃ | 3 |
CAD (KiCad official)
- Symbol:
TM4559AS - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
tm4559as-etched.step/tm4559as-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tm4559as.step/tm4559as.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Tritech MOS datasheet (8 pp, sha256
c3006d3e7e57c123, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).