# TLV9062IDGKR

**Texas Instruments** · Operational Amplifier · VSSOP-8

TLV9062IDGKR from Texas Instruments, in a VSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT1 | output | Amplifier output, channel 1. Rail-to-rail output stage; capable of driving up to 100 pF capacitive load with resistive open-loop output impedance for easier stability. |
| 2 | IN1- | input | Inverting input, channel 1. Rail-to-rail input; typical input bias current 0.5 pA. |
| 3 | IN1+ | input | Noninverting input, channel 1. Rail-to-rail input; typical input bias current 0.5 pA. |
| 4 | V- | power_in | Negative (lowest) supply rail, or GND for single-supply operation. Total supply (V+) - (V-) is 1.8 V to 5.5 V. |
| 5 | IN2+ | input | Noninverting input, channel 2. Rail-to-rail input; typical input bias current 0.5 pA. |
| 6 | IN2- | input | Inverting input, channel 2. Rail-to-rail input; typical input bias current 0.5 pA. |
| 7 | OUT2 | output | Amplifier output, channel 2. Rail-to-rail output stage; capable of driving up to 100 pF capacitive load with resistive open-loop output impedance for easier stability. |
| 8 | V+ | power_in | Positive (highest) supply rail. Total supply (V+) - (V-) is 1.8 V to 5.5 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-8 |
| Category | Op-amp/Cmp |
| Pins | 8 |

## Ordering variants

Same part, different packaging or reel option.

- `TLV9062IDGKR`
- `TLV9062IDGKT`
- `TLV9062IDGKRD`
- `TLV9062IDGKRPW`
- `TLV9062IDGKRDDF`
- `TLV9062IDGKRDSG`

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VS | 1.8 |  | 5.5 | V | VS = [V+] – [V–] | 12 |
| High level input voltage at shutdown pin (amplifier enabled) | VSHDN_IH | 1.1 |  |  | V |  | 12 |
| Low level input voltage at shutdown pin (amplifier disabled) | VSHDN_IL |  |  | 0.2 | V |  | 12 |
| Specified temperature | TA | -40 |  | 125 | °C |  | 12 |
| Supply voltage [(V+) – (V–)] | VS | 0 |  | 6 | V |  | 12 |
| Signal input pins current |  | -10 |  | 10 | mA |  | 12 |
| Specified temperature (absolute maximum) | TA | -40 |  | 125 | °C |  | 12 |
| Junction temperature | TJ |  |  | 150 | °C |  | 12 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 12 |
| Junction-to-ambient thermal resistance | RθJA |  | 201.2 |  | °C/W | DGK (VSSOP), 8 pins | 13 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 85.7 |  | °C/W | DGK (VSSOP), 8 pins | 13 |
| Junction-to-board thermal resistance | RθJB |  | 122.9 |  | °C/W | DGK (VSSOP), 8 pins | 13 |
| Junction-to-top characterization parameter | ψJT |  | 21.2 |  | °C/W | DGK (VSSOP), 8 pins | 13 |
| Junction-to-board characterization parameter | ψJB |  | 121.4 |  | °C/W | DGK (VSSOP), 8 pins | 13 |
| Input offset voltage | VOS | -1.6 | 0.3 | 1.6 | mV | VS = 5 V | 15 |
| Input offset voltage | VOS | -2 |  | 2 | mV | VS = 5 V, TA = –40°C to 125°C | 15 |
| Power-supply rejection ratio | PSRR | -80 | 7 | 80 | µV/V | VS = 1.8 V – 5.5 V, VCM = (V–) | 15 |
| Common-mode rejection ratio | CMRR | 80 | 103 |  | dB | VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V, TA = –40°C to 125°C | 15 |
| Common-mode rejection ratio | CMRR | 57 | 87 |  | dB | VS = 5.5 V, VCM = –0.1 V to 5.6 V, TA = –40°C to 125°C | 15 |
| Common-mode rejection ratio | CMRR | 88 |  |  | dB | VS = 1.8 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V, TA = –40°C to 125°C | 15 |
| Common-mode rejection ratio | CMRR | 81 |  |  | dB | VS = 1.8 V, VCM = –0.1 V to 1.9 V, TA = –40°C to 125°C | 15 |
| Open-loop voltage gain | AOL | 100 |  |  | dB | VS = 1.8 V, (V–) + 0.04 V < VO < (V+) – 0.04 V, RL = 10 kΩ | 15 |
| Open-loop voltage gain | AOL | 104 | 130 |  | dB | VS = 5.5 V, (V–) + 0.05 V < VO < (V+) – 0.05 V, RL = 10 kΩ | 15 |
| Voltage output swing from supply rails | VO |  |  | 20 | mV | VS = 5.5 V, RL = 10 kΩ | 15 |
| Voltage output swing from supply rails | VO |  |  | 60 | mV | VS = 5.5 V, RL = 2 kΩ | 15 |
| Quiescent current per amplifier | IQ |  | 538 | 750 | µA | VS = 5.5 V, IO = 0 mA | 16 |
| Quiescent current per amplifier | IQ |  |  | 800 | µA | VS = 5.5 V, IO = 0 mA, TA = –40°C to 125°C | 16 |
| Quiescent current per amplifier in shutdown | IQSD |  | 0.5 | 1.5 | µA | VS = 1.8 V to 5.5 V, all amplifiers disabled, SHDN = Low | 16 |

## CAD (KiCad official)

- Symbol: `TLV9062IDGKR`
- Footprint: `Package_SO:VSSOP-8_2.3x2mm_P0.5mm`
- 3D model: VSSOP-8 (KiCad packages3D, STEP)
- 3D model files: `tlv9062idgkr-etched.step` / `tlv9062idgkr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tlv9062idgkr.step` / `tlv9062idgkr.glb` are the bare package body.

## 3D model downloads

Two STEP files. Same geometry, different body top:

| File | Size | Use it when |
|---|---|---|
| [`tlv9062idgkr.step`](tlv9062idgkr.step) | 122 KB | You want the bare part, or you mark your own boards. |
| [`tlv9062idgkr-etched.step`](tlv9062idgkr-etched.step) | 2.3 MB | You want the part with `TLV9062IDGKR` already on it. |

The marking in the etched file is real recessed geometry cut into the solid, not a
texture or a decal: 573 faces against 147 in the bare model. It
survives export, section views, and rendering in any CAD tool, and it drops straight
into KiCad or Fusion with no extra setup.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tlv9062i.pdf) (75 pp, sha256 `424562d65438d8ae`, retrieved 2026-08-17, tier: manufacturer)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tlv9062idgkr-datasheet.pdf)