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Ray tlv9020l1dckr: CAD wording names the Adom_Gen land, not KiCad official 80d5960

TLV9020L1DCKR

Texas Instruments · Integrated Circuits (ICs) · 6-TSSOP, SC-88, SOT-363

TLV9020L1DCKR from Texas Instruments, in a 6-TSSOP, SC-88, SOT-363. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). The symbol is generated from that pin table and the footprint is an Adom_Gen land derived from the manufacturer drawing; the 3D model is generated to fit it.

Pinout

Pin Name Type Function
1 IN+ input Non-inverting (+) input of the comparator.
2 V- power_in Negative supply voltage pin.
3 IN- input Inverting (-) input of the comparator.
4 OUT output Comparator output; latches on the first threshold crossing until cleared by CLR.
5 CLR input Clear input; pulse high (> 1.2V) to clear the output latch.
6 V+ power_in Positive supply voltage pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package 6-TSSOP, SC-88, SOT-363
Category Integrated Circuits (ICs)
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input threshold voltage VT -1.75 0.3 1.75 mV VS = 1.8V and 5V 7
Input threshold voltage over temperature VT -2.25 2.25 mV VS = 1.8V and 5V, TA = -40°C to +125°C 7
Input threshold voltage drift dVT/dT -0.5 0.5 µV/°C VS = 1.8V and 5V, TA = -40°C to +125°C 7
Quiescent current per comparator IQ 22 30 µA VS = 1.8V and 5V, No Load, Output Low 7
Quiescent current per comparator over temperature IQ 42 µA VS = 1.8V and 5V, No Load, Output Low, TA = -40°C to +125°C 7
Power-supply rejection ratio (push-pull) PSRR 75 95 dB VS = 1.8V to 5V, TA = -40°C to +125°C (push-pull only) 7
Power-supply rejection ratio (open drain) PSRR 80 95 dB VS = 1.8V to 5V, TA = -40°C to +125°C (open drain only) 7
Common-mode rejection ratio (5V) CMRR 60 70 dB VS = 5V, (V-) - 0.2V < VCM < (V+) + 0.2V, TA = -40°C to +125°C 7
Common-mode rejection ratio (1.8V) CMRR 50 60 dB VS = 1.8V, (V-) - 0.2V < VCM < (V+) + 0.2V, TA = -40°C to +125°C 7
Common-mode voltage range VCM-Range -0.2 0.2 V VS = 1.8V and 5V, TA = -40°C to +125°C; min relative to (V-), max relative to (V+) 7
Voltage swing from (V-) VOL 75 125 mV ISINK = 4mA, TA = 25°C 7
Voltage swing from (V-) over temperature VOL 175 mV ISINK = 4mA, TA = -40°C to +125°C 7
Voltage swing from (V+) (push-pull) VOH 75 125 mV ISOURCE = 4mA, TA = 25°C (push-pull only) 7
Voltage swing from (V+) over temperature (push-pull) VOH 175 mV ISOURCE = 4mA, TA = -40°C to +125°C (push-pull only) 7
Short-circuit current sinking ISC 75 85 mA VS = 5V, Sinking 7
Short-circuit current sourcing (push-pull) ISC 75 85 mA VS = 5V, Sourcing (push-pull only) 7
Clear fall to latch reset propagation delay TPD-CLR-F 25 70 ns CLR = 1.8V to 5V, delay from CLR falling edge signal to unlatched output condition 8
Supply voltage VS 1.65 5.5 V VS = (V+) - (V-) 5
Input voltage range (IN+, IN-, CLR) -0.2 5.5 V from (V-) 5
Input common mode voltage range (IN+, IN-) -0.2 0.2 V min from (V-), max (V+) + 0.2 V 5
Output voltage range, open drain output 0 5.5 V from (V-) 5
Ambient temperature TA -40 125 °C 5
Supply voltage VS -0.3 6 V VS = (V+) - (V-) 5
Input pins voltage (IN+, IN-, CLR) -0.3 6 V from (V-) 5
Current into input pins (IN+, IN-, CLR) -10 10 mA 5
Output (OUT) voltage -0.3 6 V from (V-) 5
Output (OUT) open drain voltage -0.3 V from (V-); upper limit is (V+) + 0.3 V as printed 5
Output short circuit duration 10 s Short-circuit to (V-) or (V+) 5
Junction temperature TJ 150 °C 5
Storage temperature Tstg -65 150 °C 5
ESD human-body model V(ESD) -2000 2000 V HBM, per ANSI/ESDA/JEDEC JS-001 5
ESD charged-device model V(ESD) -1000 1000 V CDM, per ANSI/ESDA/JEDEC JS-002 5
Junction-to-ambient thermal resistance (DCK) RqJA 210.5 °C/W DCK (SC-70) package, single 6
Junction-to-case (top) thermal resistance (DCK) RqJC(top) 143.9 °C/W DCK (SC-70) package, single 6
Junction-to-board thermal resistance (DCK) RqJB 64.7 °C/W DCK (SC-70) package, single 6
Junction-to-top characterization parameter (DCK) yJT 46.1 °C/W DCK (SC-70) package, single 6
Junction-to-board characterization parameter (DCK) yJB 64.5 °C/W DCK (SC-70) package, single 6

CAD (Adom-generated)

  • Symbol: TLV9020L1DCKR
  • Footprint: Adom_Gen:Texas_Instruments_TLV9020
  • 3D model: generated to fit the land (STEP)
  • 3D model files: tlv9020l1dckr-etched.step / tlv9020l1dckr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv9020l1dckr.step / tlv9020l1dckr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (40 pp, sha256 a8706fdf8ff72411, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: symbol generated from the datasheet pin table; footprint an Adom_Gen land derived from the manufacturer drawing. 3D model generated to fit that land.

Datasheet PDF