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TLV840NAPL50DBVR

Texas Instruments · Supervisor And Reset ICs · SOT-23-5

TLV840NAPL50DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RESET output Active-low push-pull reset output that is driven low when VDD falls below VIT- and stays low for the reset delay tD after VDD rises above VIT+; RESET pin current is limited to ±5 mA recommended and ±20 mA absolute maximum.
2 VDD power_in Supply input whose voltage is monitored by the device, with a recommended range of 0.7 V to 6 V and an absolute maximum of 6.5 V.
3 GND power_in Ground reference pin for the device.
4 NC unconnected No connect on the TLV840N; the pin can be left floating, and the datasheet recommends connecting it to GND.
5 NC unconnected No connect on the TLV840N; the pin can be left floating, and the datasheet recommends connecting it to GND.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Power Management (PMIC)
Pins 5

CAD (KiCad official)

  • Symbol: TLV840NAPL50DBVR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tlv840napl50dbvr-etched.step / tlv840napl50dbvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv840napl50dbvr.step / tlv840napl50dbvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 a8df9af31101d134, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF