# TLV840MADL40DBVRQ1

**Texas Instruments** · Supervisor And Reset ICs · SOT-23-5

TLV840MADL40DBVRQ1 from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RESET | output | Open-drain active-low reset output that is driven logic low when VDD falls below VIT- and stays low for the delay time tD after VDD rises above VIT+ = VIT- + VHYS. |
| 2 | VDD | power_in | Input supply voltage that the device monitors; recommended operating range is 0.7 V to 6 V with an absolute maximum of 6.5 V. |
| 3 | GND | power_in | Ground reference pin for the device. |
| 4 | MR | input | Manual reset input; pulling it to logic low asserts RESET, and when it is floating or logic high, RESET deasserts after the reset delay time tD expires. |
| 5 | CT | passive | Capacitor time-delay pin used to program tD by connecting an external capacitor to GND; when left floating it gives the smallest fixed delay (40 µs typ). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input supply voltage VDD | VDD | 0.7 |  | 6 | V | TLV840MAxL | 6 |
| Negative-going input threshold accuracy VIT- = 1.8 V to 5.4 V | VIT- | -2 | 0.5 | 2 | % | VIT- = 1.8 V to 5.4 V | 6 |
| Hysteresis on VIT- pin | VHYS | 2.5 | 5 | 7 | % |  | 6 |
| Supply current into VDD pin | IDD |  | 0.15 | 1.2 | µA | VDD = 6 V; VIT- = 0.8 V to 5.4 V | 6 |
| Manual reset logic low input | VMR_L |  |  | 0.3 | V | 0.3VDD | 6 |
| Manual reset logic high input | VMR_H | 0.7 |  |  | V | 0.7VDD | 6 |
| Manual reset internal pull-up resistance | RMR |  | 100 |  | kΩ |  | 6 |
| CT pin internal resistance | RCT |  | 500 |  | kΩ |  | 6 |
| Power on Reset Voltage (TLV840MADL) | VPOR |  |  | 700 | mV | VOL(max) = 300 mV; IOUT(Sink) = 15 µA | 6 |
| Low level output voltage (TLV840MADL, VDD=3.3 V, 3.4 V ≤ VIT- ≤ 5.5 V) | VOL |  |  | 300 | mV | VDD = 3.3 V, 3.4 V ≤ VIT- ≤ 5.5 V; IOUT(Sink) = 2 mA | 6 |
| Open-drain output leakage current (TA = -40 to 85 °C) | Ilkg(OD) |  | 10 | 100 | nA | VDD = VPULLUP = 6V; TA = -40℃ to 85℃ | 6 |
| Open-drain output leakage current (full temperature range) | Ilkg(OD) |  | 10 | 350 | nA | VDD = VPULLUP = 6V | 6 |
| Propagation detect delay for VDD falling below VIT- | tP_HL |  | 30 | 50 | µs | VDD : (VIT+ + 10%) to (VIT-, 10%) | 7 |
| Reset time delay (CT pin open or NC) | tD | 40 |  | 80 | µs | CT pin = Open or NC; (VIT- - 10%) to (VIT+ + 10%) | 7 |
| Voltage absolute maximum VDD | VDD | -0.3 |  | 6.5 | V |  | 5 |
| Voltage RESET (TLV840MADL) | VRESET | -0.3 |  | 6.5 | V | RESET (TLV840MADL) | 5 |
| Current RESET, RESET pin | I | -20 |  | 20 | mA | RESET, RESET pin | 5 |
| Operating ambient temperature | TA | -40 |  | 125 | ℃ |  | 5 |
| Storage temperature | Tstg | -65 |  | 150 | ℃ |  | 5 |
| Voltage CT, MR, RESET (TLV840MAPL/MAPH) | V | -0.3 |  |  | V | Max is VDD+0.3 (or 6.5 V, whichever is smaller); applies to CT, MR, RESET (TLV840MAPL), RESET (TLV840MAPH) | 5 |
| Current RESET and RESET pin current | I | -5 |  | 5 | mA | RESET and RESET pin current | 5 |
| Voltage CT, RESET (TLV840MAxL), RESET (TLV840MAPH), MR | V | 0 |  | 6 | V | CT, RESET (TLV840MAxL), RESET (TLV840MAPH), MR | 5 |
| Operating ambient temperature (recommended) | TA | -40 |  | 125 | ℃ |  | 5 |
| Junction-to-ambient thermal resistance | RθJA |  | 193.5 |  | °C/W | DBV (SOT23-5) | 5 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 117.9 |  | °C/W | DBV (SOT23-5) | 5 |
| Junction-to-board thermal resistance | RθJB |  | 98.5 |  | °C/W | DBV (SOT23-5) | 5 |
| Junction-to-top characterization parameter | ψJT |  | 43.4 |  | °C/W | DBV (SOT23-5) | 5 |
| Junction-to-board characterization parameter | ψJB |  | 97.8 |  | °C/W | DBV (SOT23-5) | 5 |

## CAD (KiCad official)

- Symbol: `TLV840MADL40DBVRQ1`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files: `tlv840madl40dbvrq1-etched.step` / `tlv840madl40dbvrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tlv840madl40dbvrq1.step` / `tlv840madl40dbvrq1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tlv840-q1) (34 pp, sha256 `5dd9e796b7333fcf`, retrieved 2026-11-06, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tlv840madl40dbvrq1-datasheet.pdf)