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Contents

README

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TLV840MADL22DBVRQ1

Texas Instruments · Supervisor And Reset ICs · SOT-23-5

TLV840MADL22DBVRQ1 from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RESET tri_state Active-low open-drain reset output; asserted low when VDD falls below VIT-, deasserted after tD delay when VDD rises above VIT+.
2 VDD power_in Input supply voltage (0.7-6 V operating range) monitored by internal comparator; quiescent current typically 0.12-1.2 µA.
3 GND power_in Ground reference pin.
4 MR input Manual reset input with internal 100 kΩ pull-up resistor; pull to logic low (≤0.3VDD) with ≥500 ns pulse to force reset output low.
5 CT passive Capacitor time delay pin with internal 500 kΩ resistor; connect external capacitor (max 10 µF) to ground for programmable reset delay from 40 µs to 6.2 seconds.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Power Management (PMIC)
Pins 5

CAD (KiCad official)

  • Symbol: TLV840MADL22DBVRQ1
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tlv840madl22dbvrq1-etched.step / tlv840madl22dbvrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv840madl22dbvrq1.step / tlv840madl22dbvrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (33 pp, sha256 1398027069db3ad2, retrieved 2026-09-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF