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Contents

README

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TLV840CADL14DBVR

Texas Instruments · Supervisor And Reset ICs · SOT-23-5

TLV840CADL14DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RESET tri_state Active-low open-drain reset output driven low when VDD falls below the negative voltage threshold (VIT-); remains low for the reset delay time (tD) after VDD rises above VIT- + VHYS.
2 VDD power_in Supply voltage input monitored by the TLV840 for voltage supervision; recommended operating range 0.7 V to 6 V.
3 GND power_in Ground reference.
4 NC unconnected No Connect pin for TLV840C variant; can be left floating or connected to GND.
5 CT passive Capacitor Time Delay pin for user-programmable reset delay; connect external capacitor to adjust delay or leave floating for 40 µs minimum delay.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Power Management (PMIC)
Pins 5

CAD (KiCad official)

  • Symbol: TLV840CADL14DBVR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tlv840cadl14dbvr-etched.step / tlv840cadl14dbvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv840cadl14dbvr.step / tlv840cadl14dbvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 a8df9af31101d134, retrieved 2026-10-06, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF