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Contents

README

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TLV77325PDBVR

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

TLV77325PDBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Input voltage supply, specified at 1.4 V to 5.5 V in the Recommended Operating Conditions, with a 1 µF nominal input capacitor placed as close to the IN and GND pins as possible.
2 GND power_in Common ground, to which all voltages in the datasheet are referenced.
3 EN input Enable input: a voltage below VEN(LOW) turns the regulator off and discharges the output to GND, and a voltage above VEN(HI) enables the regulated output, with VEN rated 0 V to 5.5 V.
4 N/C unconnected No internal electrical connection; the datasheet recommends connecting this pin to GND for improved thermal performance.
5 OUT output Regulated output voltage that requires a low-ESR capacitor from OUT to ground (0.47 µF to 40 µF effective, ESR up to 100 mΩ), with an internal pulldown that discharges VOUT in shutdown.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Power Management (PMIC)
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input supply voltage VIN 1.4 5.5 V 4
Enable input voltage VEN 0 5.5 V 4
Nominal output voltage range (family range, not specific to 2.5V variant) VOUT 0.6 3.3 V 4
Output current IOUT 0 300 mA 4
Output capacitance (effective) COUT 0.47 40 µF Effective output capacitance 4
Output capacitor effective series resistance ESR 100 mΩ 4
Operating junction temperature TJ -40 125 °C 4
Input voltage VIN -0.3 6.5 V Relative to GND 4
Output voltage VOUT -0.3 6 V Maximum is the lesser of 6.0 V or VIN + 0.3 V 4
Enable voltage VEN -0.3 6.5 V Relative to GND 4
Operating junction temperature TJ -55 150 °C 4
Storage temperature Tstg -65 150 °C 4
Output voltage tolerance ΔVOUT -2 2 % 1.8V ≤ VOUT ≤ 3.3V 5
Output voltage tolerance ΔVOUT -2.5 2.5 % TJ = -40°C to 85°C, 2.5V ≤ VOUT ≤ 3.3V 5
Line regulation ΔVOUT / ΔVIN 0.01 0.1 %/V VIN = (VOUT(NOM) + 0.5V) to 5.5V 5
Load regulation ΔVOUT / ΔIOUT 85 110 µV/mA IOUT = 1mA to 300mA 5
Quiescent ground current IGND 80 120 µA VEN = VIN = 5.5V, IOUT = 0mA, TJ = -40°C to 85°C 5
Shutdown ground current ISHDN 0.01 2 µA VEN < VEN(LOW), VIN = 5.5V, TJ = -40°C to 85°C 5
Dropout voltage VDO 245 mV IOUT = 300mA, VIN = VOUT(NOM), 2.5V ≤ VOUT < 2.8V 5
Dropout voltage VDO 285 mV IOUT = 300mA, VIN = VOUT(NOM), TJ = -40°C to 85°C, 2.5V ≤ VOUT < 2.8V 5
Output current limit ICL 350 720 mA VOUT = 0.9 x VOUT(NOM), TJ = -40°C to 85°C 5
Low input threshold VEN(LOW) 0.3 V VEN falling until the output is disabled, TJ = -40°C to 85°C 6
High input threshold VEN(HI) 0.9 V VEN rising until the output is enabled, TJ = -40°C to 85°C 6
EN input leakage current IEN 0.01 1 µA VEN = 5.5V and VIN = 5.5V 6
Start-up time (VEN) tSTR 400 µs From VEN > VEN(HI) to VOUT = 95% of VOUT(NOM), VIN rise time = 1V/µs 6
Input capacitor CIN 1 µF 4
Short-circuit current limit ISC 65 mA VOUT = 0V 5
Output automatic discharge pulldown resistance RPULLDOWN 135 Ω VEN < VEN(LOW) (output disabled), VIN = 3.3V 5
Power-supply rejection ratio PSRR 80 dB IOUT = 1mA, VIN = VOUT + 1.0V, f = 217Hz 5
Power-supply rejection ratio PSRR 72 dB IOUT = 1mA, VIN = VOUT + 1.0V, f = 1kHz 5
Power-supply rejection ratio PSRR 56 dB IOUT = 50mA, VIN = VOUT + 1.0V, f = 100kHz 5
Power-supply rejection ratio PSRR 55 dB IOUT = 50mA, VIN = VOUT + 1.0V, f = 1MHz 5
Thermal shutdown (TJ rising) TSD 160 °C TJ rising 6
Thermal shutdown (TJ falling) TSD 140 °C TJ falling 6
Junction-to-ambient thermal resistance RθJA 242.5 °C/W DBV (SOT-23, 5 pins) 5
Junction-to-case (top) thermal resistance RθJC(top) 140.9 °C/W DBV (SOT-23, 5 pins) 5
Junction-to-board thermal resistance RθJB 109.4 °C/W DBV (SOT-23, 5 pins) 5
Junction-to-top characterization parameter ψJT 76.1 °C/W DBV (SOT-23, 5 pins) 5
Junction-to-board characterization parameter ψJB 108.8 °C/W DBV (SOT-23, 5 pins) 5

CAD (KiCad official)

  • Symbol: TLV77325PDBVR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tlv77325pdbvr-etched.step / tlv77325pdbvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv77325pdbvr.step / tlv77325pdbvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (32 pp, sha256 ca5860361e44f9bd, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF