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TLV77312PDBVR

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TI(德州仪器) Global Sourcing Parts, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TLV77312PDBVR

TI(德州仪器) · Global Sourcing Parts · SOT-23-5

TLV77312PDBVR from TI(德州仪器), in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Input voltage supply with a recommended operating range of 1.4 V to 5.5 V, and a nominal 1 µF input capacitor should be placed as close to the IN and GND pins as possible.
2 GND power_in Common ground.
3 EN input Enable input: a voltage below VEN(LOW) turns the regulator off and discharges the output to GND, while a voltage above VEN(HI) enables the regulator output.
4 N/C unconnected No internal electrical connection; the datasheet recommends connecting this pin to GND for improved thermal performance.
5 OUT power_out Regulated output voltage that requires a low-ESR capacitor from OUT to ground for stability, and an internal pulldown resistor discharges VOUT when the regulator is in shutdown.

Key specifications

Parameter Value
Manufacturer TI(德州仪器)
Package SOT-23-5
Category Global Sourcing Parts
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage supply (absolute maximum) VIN -0.3 6.5 V With respect to GND 4
Output voltage (absolute maximum) VOUT -0.3 6 V Max is lesser of 6.0V or VIN + 0.3V (footnote 2) 4
Enable voltage (absolute maximum) VEN -0.3 6.5 V With respect to GND 4
Operating junction temperature (absolute maximum) TJ -55 150 °C 4
Storage temperature Tstg -65 150 °C 4
ESD human-body model (HBM) V(ESD) -1000 1000 V HBM, per ANSI/ESDA/JEDEC JS-001 4
ESD charged-device model (CDM) V(ESD) -500 500 V CDM, per JEDEC JESD22-C101 4
Input supply voltage VIN 1.4 5.5 V 4
Enable input voltage VEN 0 5.5 V 4
Nominal output voltage range VOUT 0.6 3.3 V Device family range; this part is 1.2V 4
Output current IOUT 0 300 mA 4
Output capacitance COUT 0.47 40 µF Effective output capacitance (footnote 3) 4
Output capacitor effective series resistance ESR 100 mΩ 4
Operating junction temperature TJ -40 125 °C 4
Output voltage tolerance ΔVOUT -2.5 2.5 % 0.6V ≤ VOUT < 1.8V, TJ = 25°C 5
Output voltage tolerance ΔVOUT -3 3 % 1.2V ≤ VOUT < 1.8V, TJ = -40°C to 85°C 5
Line regulation ΔVOUT / ΔVIN 0.01 0.1 %/V VIN = (VOUT(NOM) + 0.5V) to 5.5V 5
Load regulation ΔVOUT / ΔIOUT 85 110 µV/mA IOUT = 1mA to 300mA 5
Quiescent ground current IGND 80 120 µA VEN = VIN = 5.5V, IOUT = 0mA, TJ = -40°C to 85°C 5
Shutdown ground current ISHDN 0.01 2 µA VEN < VEN(LOW), VIN = 5.5V, TJ = -40°C to 85°C 5
Dropout voltage VDO 600 mV IOUT = 300mA, VIN = VOUT(NOM), 1.05V ≤ VOUT < 1.8V (footnotes 1, 2) 5
Dropout voltage VDO 680 mV IOUT = 300mA, VIN = VOUT(NOM), 1.05V ≤ VOUT < 1.8V, TJ = -40°C to 85°C (footnotes 1, 2) 5
Output current limit ICL 350 720 mA VOUT = 0.9 x VOUT(NOM), TJ = -40°C to 85°C 5
Low input threshold VEN(LOW) 0.3 V VEN falling until the output is disabled, TJ = -40°C to 85°C 6
High input threshold VEN(HI) 0.9 V VEN rising until the output is enabled, TJ = -40°C to 85°C 6
EN input leakage current IEN 0.01 1 µA VEN = 5.5V and VIN = 5.5V 6
Start-up time tSTR 400 µs From VEN > VEN(HI) to VOUT = 95% of VOUT(NOM), VIN rise time = 1V/µs 6
Short-circuit current limit ISC 65 mA VOUT = 0V 5
Power-supply rejection ratio PSRR 80 dB IOUT = 1mA, VIN = VOUT + 1.0V, f = 217Hz 5
Power-supply rejection ratio PSRR 72 dB IOUT = 1mA, VIN = VOUT + 1.0V, f = 1kHz 5
Power-supply rejection ratio PSRR 56 dB IOUT = 50mA, VIN = VOUT + 1.0V, f = 100kHz 5
Power-supply rejection ratio PSRR 55 dB IOUT = 50mA, VIN = VOUT + 1.0V, f = 1MHz 5
Output automatic discharge pulldown resistance RPULLDOWN 135 Ω VEN < VEN(LOW) (output disabled), VIN = 3.3V 5
Thermal shutdown (rising) TSD 160 °C TJ rising 6
Thermal shutdown (falling) TSD 140 °C TJ falling 6
Input capacitor CIN 1 µF Printed as single value 4
Junction-to-ambient thermal resistance (DBV) RθJA 242.5 °C/W DBV (SOT-23), 5 pins 5
Junction-to-case (top) thermal resistance (DBV) RθJC(top) 140.9 °C/W DBV (SOT-23), 5 pins 5
Junction-to-board thermal resistance (DBV) RθJB 109.4 °C/W DBV (SOT-23), 5 pins 5
Junction-to-top characterization parameter (DBV) ψJT 76.1 °C/W DBV (SOT-23), 5 pins 5
Junction-to-board characterization parameter (DBV) ψJB 108.8 °C/W DBV (SOT-23), 5 pins 5

CAD (KiCad official)

  • Symbol: TLV77312PDBVR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tlv77312pdbvr-etched.step / tlv77312pdbvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv77312pdbvr.step / tlv77312pdbvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TI(德州仪器) datasheet (32 pp, sha256 ca5860361e44f9bd, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF