component
TLV77118PDBVR
Public Made by Adomby adom
Texas Instruments , SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTLV77118PDBVR
Texas Instruments · IC · SOT-23-5
TLV77118PDBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Input voltage supply (1.4V to 5.5V recommended); place the input capacitor (1µF nominal) as close to IN and GND as possible for best transient response. |
| 2 | GND | power_in | Common ground. |
| 3 | EN | input | Enable input: a voltage below VEN(LOW) turns the regulator off and discharges the output to GND, and a voltage above VEN(HI) enables the output. |
| 4 | N/C | unconnected | No internal electrical connection; connect to GND for improved thermal performance. |
| 5 | OUT | power_out | Regulated output voltage; requires a low-ESR output capacitor (0.47µF to 40µF effective) to ground for stability, and an internal pulldown resistor discharges VOUT in shutdown. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output voltage tolerance | ΔVOUT | -2 | 2 | % | 1.8V ≤ VOUT ≤ 3.3V | 5 | |
| Output voltage tolerance over temperature | ΔVOUT | -2.75 | 2.75 | % | TJ = -40℃ to 85℃, 1.8V ≤ VOUT < 2.5V | 5 | |
| Line regulation | ΔVOUT | 0.01 | 0.1 | %/V | VIN = (VOUT(NOM) + 0.5V) to 5.5V | 5 | |
| Load regulation | ΔVOUT | 85 | 110 | µV/mA | IOUT = 1mA to 150mA | 5 | |
| Quiescent ground current | IGND | 80 | 120 | µA | VEN = VIN = 5.5V, IOUT = 0 mA, TJ = -40°C to 85°C | 5 | |
| Shutdown ground current | ISHDN | 0.01 | 2 | µA | VEN < VEN(LOW), VIN = 5.5 V, TJ = -40°C to 85°C | 5 | |
| Dropout voltage | VDO | 170 | 195 | mV | IOUT = 150mA, VIN = 95% × VOUT(NOM), 1.8V ≤ VOUT < 2.5V; max for TJ = -40°C to 85°C | 5 | |
| EN input leakage current | IEN | 0.01 | 1 | µA | VEN = 5.5V and VIN = 5.5V | 5 | |
| Short-circuit current limit | ISC | 42 | mA | VOUT = 0V | 5 | ||
| Power-supply rejection ratio | PSRR | 56 | dB | IOUT = 50mA, VIN = VOUT + 1.0V, f = 100kHz | 5 | ||
| Power-supply rejection ratio | PSRR | 55 | dB | IOUT = 50mA, VIN = VOUT + 1.0V, f = 1MHz | 5 | ||
| Output noise voltage | VN | 90 | µVRMS | BW = 10Hz to 100kHz, VOUT = 1.2V, IOUT = 50mA | 5 | ||
| Output automatic discharge pulldown resistance | RPULLDOWN | 135 | Ω | VEN < VEN(LOW) (output disabled), VIN = 3.3V | 5 | ||
| Thermal shutdown, rising | TSD | 160 | °C | TJ rising | 5 | ||
| Thermal shutdown, falling | TSD | 140 | °C | TJ falling | 5 | ||
| Input voltage, absolute maximum | VIN | -0.3 | 6.5 | V | 4 | ||
| Output voltage, absolute maximum | VOUT | -0.3 | 6 | V | Lesser of 6.0V or VIN + 0.3V | 4 | |
| Enable voltage, absolute maximum | VEN | -0.3 | 6.5 | V | 4 | ||
| Operating junction temperature, absolute maximum | TJ | -55 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| ESD HBM | V(ESD) | -1000 | 1000 | V | Human-body model, ANSI/ESDA/JEDEC JS-001 | 4 | |
| ESD CDM | V(ESD) | -500 | 500 | V | Charged-device model, JESD22-C101 | 4 | |
| Input supply voltage | VIN | 1.4 | 5.5 | V | 4 | ||
| Enable input voltage | VEN | 0 | 5.5 | V | 4 | ||
| Output current | IOUT | 0 | 150 | mA | 4 | ||
| Input capacitor | CIN | 1 | µF | 4 | |||
| Output capacitance | COUT | 0.47 | 40 | µF | Effective output capacitance | 4 | |
| Output capacitor ESR | ESR | 100 | mΩ | 4 | |||
| Operating junction temperature | TJ | -40 | 125 | °C | 4 | ||
| Junction-to-ambient thermal resistance | RθJA | 242.5 | °C/W | DBV (SOT-23), 5 pins | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 140.9 | °C/W | DBV (SOT-23), 5 pins | 5 | ||
| Junction-to-board thermal resistance | RθJB | 109.4 | °C/W | DBV (SOT-23), 5 pins | 5 | ||
| Junction-to-top characterization parameter | ψJT | 76.1 | °C/W | DBV (SOT-23), 5 pins | 5 | ||
| Junction-to-board characterization parameter | ψJB | 108.8 | °C/W | DBV (SOT-23), 5 pins | 5 |
CAD (KiCad official)
- Symbol:
TLV77118PDBVR - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
tlv77118pdbvr-etched.step/tlv77118pdbvr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlv77118pdbvr.step/tlv77118pdbvr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (29 pp, sha256
dad4ed74454c5a6d, retrieved 2026-10-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).