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TLV77033PDBVR

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Texas Instruments , SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TLV77033PDBVR

Texas Instruments · IC · SOT-23-5

TLV77033PDBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Input voltage supply with a VIN range of 1.4 V to 5.5 V; use the nominal or larger input capacitor from IN to ground, placed as close to the IN and GND pins as possible.
2 GND power_in Common ground; all voltages are specified with respect to this pin.
3 EN input Enable input: a voltage below VEN(LOW) turns the regulator off and discharges OUT to GND, a voltage above VEN(HI) enables the output, and the pin is rated 0 V to 5.5 V.
4 N/C unconnected No internal electrical connection; connect to GND for improved thermal performance.
5 OUT power_out Regulated output voltage (0.6 V to 3.3 V nominal) requiring a low-ESR capacitor from OUT to ground (0.47 µF to 40 µF effective, ESR up to 100 mΩ), with an internal pulldown that discharges the output in shutdown.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output voltage tolerance (1.8V ≤ VOUT ≤ 3.3V) ΔVOUT -2 2 % 1.8V ≤ VOUT ≤ 3.3V 5
Output voltage tolerance over TJ (2.5V ≤ VOUT ≤ 3.3V) ΔVOUT -2.5 2.5 % TJ = -40℃ to 85℃, 2.5V ≤ VOUT ≤ 3.3V 5
Dropout voltage over TJ VDO 50 mV IOUT = 50mA, VIN = 95% × VOUT(NOM), TJ = -40°C to 85°C, 2.5V ≤ VOUT ≤ 3.3V 5
Output current limit ICL 80 210 mA VOUT = 0.9 x VOUT(NOM), TJ = -40°C to 85°C 5
Enable low input threshold VEN(LOW) 0.3 V VEN falling until the output is disabled, TJ = -40°C to 85°C 5
Enable high input threshold VEN(HI) 0.9 V VEN rising until the output is enabled, TJ = -40°C to 85°C 5
Quiescent ground current IGND 80 120 µA VEN = VIN = 5.5V, IOUT = 0mA, TJ = -40°C to 85°C 5
Shutdown ground current ISHDN 0.01 2 µA VEN < VEN(LOW), VIN = 5.5V, TJ = -40°C to 85°C 5
Line regulation ΔVOUT 0.01 0.1 %/V VIN = (VOUT(NOM) + 0.5V) to 5.5V 5
Load regulation ΔVOUT 85 110 µV/mA IOUT = 1mA to 50mA 5
Enable input leakage current IEN 0.01 1 µA VEN = 5.5V and VIN = 5.5V 5
Dropout voltage (25°C) VDO 45 mV IOUT = 50mA, VIN = 95% × VOUT(NOM), 2.5V ≤ VOUT ≤ 3.3V 5
Power-supply rejection ratio (100kHz) PSRR 56 dB IOUT = 50mA, VIN = VOUT + 1.0V, f = 100kHz 5
Power-supply rejection ratio (1MHz) PSRR 55 dB IOUT = 50mA, VIN = VOUT + 1.0V, f = 1MHz 5
Output noise voltage VN 90 µVRMS BW = 10Hz to 100kHz, VOUT = 1.2V, IOUT = 50mA 5
Output automatic discharge pulldown resistance RPULLDOWN 135 Ω VEN < VEN(LOW) (output disabled), VIN = 3.3V 5
Thermal shutdown (TJ rising) TSD 160 °C TJ rising 5
Thermal shutdown (TJ falling) TSD 140 °C TJ falling 5
Start-up time (VEN) tSTR 320 µs From VEN > VEN(HI) to VOUT = 95% of VOUT(NOM), VIN rise time = 1V/µs 6
Input supply voltage VIN 1.4 5.5 V 4
Enable input voltage VEN 0 5.5 V 4
Nominal output voltage range VOUT 0.6 3.3 V 4
Output current IOUT 0 50 mA 4
Output capacitance COUT 0.47 40 µF 4
Output capacitor effective series resistance ESR 100 mΩ 4
Operating junction temperature TJ -40 125 °C 4
Input capacitor CIN 1 µF 4
Input supply voltage (absolute maximum) VIN -0.3 6.5 V Voltages with respect to GND 4
Output voltage (absolute maximum) VOUT -0.3 6 V Maximum is the lesser of 6.0V or VIN + 0.3V 4
Enable voltage (absolute maximum) VEN -0.3 6.5 V Voltages with respect to GND 4
Operating junction temperature (absolute maximum) TJ -55 150 °C 4
Storage temperature Tstg -65 150 °C 4
Electrostatic discharge, human-body model V(ESD) -1000 1000 V HBM, per ANSI/ESDA/JEDEC JS-001 4
Electrostatic discharge, charged-device model V(ESD) -500 500 V CDM, per JEDEC JESD22-C101 4
Junction-to-ambient thermal resistance (DBV) RθJA 242.5 °C/W DBV (SOT-23), 5 pins 5
Junction-to-case (top) thermal resistance (DBV) RθJC(top) 140.9 °C/W DBV (SOT-23), 5 pins 5
Junction-to-board thermal resistance (DBV) RθJB 109.4 °C/W DBV (SOT-23), 5 pins 5
Junction-to-top characterization parameter (DBV) ψJT 76.1 °C/W DBV (SOT-23), 5 pins 5
Junction-to-board characterization parameter (DBV) ψJB 108.8 °C/W DBV (SOT-23), 5 pins 5

CAD (KiCad official)

  • Symbol: TLV77033PDBVR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tlv77033pdbvr-etched.step / tlv77033pdbvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv77033pdbvr.step / tlv77033pdbvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (29 pp, sha256 381d3cf560a525e8, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF