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TLV76750QWDRBRQ1
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, WSON-8-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownTLV76750QWDRBRQ1
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · WSON-8-EP(3x3)
TLV76750QWDRBRQ1 from Texas Instruments, in a WSON-8-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | output | Output pin; use the recommended output capacitor listed in the Recommended Operating Conditions table, placed as close to the OUT and GND pins as possible. |
| 2 | NC | unconnected | Not internally connected; this pin can be floated or connected to GND for best thermal performance. |
| 3 | SNS | input | Output sense pin; connect to OUT, or connect to the load to sense the output remotely, and do not float this pin (fixed-voltage versions only). |
| 4 | GND | power_in | Ground pin; all ground pins must be grounded. |
| 5 | EN | input | Enable pin; driving it high enables the device and driving it low disables the device, with high and low thresholds listed in the Electrical Characteristics table. |
| 6 | GND | power_in | Ground pin; all ground pins must be grounded. |
| 7 | NC | unconnected | Not internally connected; this pin can be floated or connected to GND for best thermal performance. |
| 8 | IN | power_in | Input pin; use the recommended input capacitor listed in the Recommended Operating Conditions table, placed as close to the IN and GND pins as possible. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-8-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage | VIN | 2.5 | 16 | V | 5 | ||
| Enable voltage | VEN | 0 | 16 | V | 5 | ||
| Output current | IOUT | 0 | 1 | A | 5 | ||
| Output capacitor | COUT | 1 | 2.2 | 220 | µF | Effective output capacitance; footnote: 0.5 µF minimum required for stability | 5 |
| Output capacitor ESR | COUT ESR | 2 | 500 | mΩ | 5 | ||
| Ambient temperature range | TA | -40 | 125 | °C | 5 | ||
| Junction temperature range | TJ | -40 | 150 | °C | 5 | ||
| Input pin voltage | VIN | -0.3 | 18 | V | All voltages with respect to GND | 4 | |
| Output pin voltage | VOUT | -0.3 | V | Max is VIN + 0.3 V or 18 V, whichever is smaller | 4 | ||
| Sense pin voltage | SNS | -0.3 | V | Fixed version; max is VIN + 0.3 V or 18 V, whichever is smaller | 4 | ||
| Enable pin voltage | EN | -0.3 | 18 | V | 4 | ||
| Ambient temperature | TA | -40 | 125 | °C | Operating free-air temperature range | 4 | |
| Operating junction temperature | TJ | -50 | 150 | °C | 4 | ||
| Storage temperature | TSTG | -65 | 150 | °C | 4 | ||
| Output accuracy at TJ = 25°C | VOUT | -0.5 | 0.5 | % | TJ = 25°C | 6 | |
| Output accuracy over temperature | VOUT | -1 | 1 | % | TJ = -40°C to 150°C, VIN ≥ 3.0 V, 1 mA ≤ IOUT ≤ 1 A | 6 | |
| Output accuracy over temperature, low input | VOUT | -1 | 1 | % | TJ = -40°C to 150°C, 2.5 V ≤ VIN < 3.0 V, 1 mA ≤ IOUT ≤ 800 mA | 6 | |
| Load regulation | ΔVOUT(ΔIOUT) | 0.1 | 0.5 | %/A | 1 mA ≤ IOUT ≤ 1 A, VIN ≥ 3.0 V | 6 | |
| Load regulation, low input | ΔVOUT(ΔIOUT) | 0.1 | 0.5 | %/A | 1 mA ≤ IOUT ≤ 800 mA, 2.5 V ≤ VIN < 3.0 V | 6 | |
| Dropout voltage | VDO | 0.63 | 0.94 | 1.5 | V | VIN(NOM) ≥ 3.0 V, IOUT = 1 A | 6 |
| Dropout voltage, low input | VDO | 0.48 | 0.8 | 1.4 | V | 2.5 V ≤ VIN(NOM) < 3.0 V, IOUT = 800 mA | 6 |
| Output current limit | ICL | 1.1 | 1.37 | 1.6 | A | VOUT = 0.9 x VOUT(NOM), VIN ≥ 3.0 V | 6 |
| Output current limit, low input | ICL | 0.81 | 1.28 | 1.6 | A | VOUT = 0.9 x VOUT(NOM), 2.5 V ≤ VIN < 3.0 V | 6 |
| Short-circuit current limit | ISC | 150 | 250 | 350 | mA | VOUT = 0 V | 6 |
| Quiescent current | IQ | 25 | 60 | 95 | µA | Fixed output devices, IOUT = 0 mA | 6 |
| Ground current | IGND | 1.5 | mA | IOUT = 1 A, VIN ≥ 3.0 V | 6 | ||
| Shutdown current | ISHUTDOWN | 0.1 | 1.6 | 4 | µA | VEN ≤ 0.4 V, VIN = 16 V | 6 |
| Enable pin logic high | VEN(HIGH) | 1.2 | V | 2.5 V ≤ VIN ≤ 16 V | 6 | ||
| Enable pin logic low | VEN(LOW) | 0.4 | V | 2.5 V ≤ VIN ≤ 16 V | 6 | ||
| Enable pullup current | IEN | 200 | 400 | 800 | nA | VEN = 0 V | 6 |
| Output pulldown current | IPULLDOWN | 0.9 | 1.4 | 1.6 | mA | VIN = 16 V, VOUT = 2.5 V, VEN = 0 V | 6 |
| UVLO threshold rising | VUVLO+ | 2 | 2.22 | 2.4 | V | VIN rising | 6 |
| UVLO threshold falling | VUVLO- | 1.9 | 2.09 | 2.3 | V | VIN falling | 6 |
| UVLO hysteresis | VUVLO(HYS) | 100 | 130 | 200 | mV | 6 | |
| Junction-to-ambient thermal resistance | RθJA | 51.9 | °C/W | DRB (VSON) 8-pin | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 66.2 | °C/W | DRB (VSON) 8-pin | 5 | ||
| Junction-to-board thermal resistance | RθJB | 24.4 | °C/W | DRB (VSON) 8-pin | 5 | ||
| Junction-to-top characterization parameter | ΨJT | 2.7 | °C/W | DRB (VSON) 8-pin | 5 | ||
| Junction-to-board characterization parameter | ΨJB | 24.3 | °C/W | DRB (VSON) 8-pin | 5 | ||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 6.9 | °C/W | DRB (VSON) 8-pin | 5 | ||
| Input capacitor | CIN | 1 | µF | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | • Use copper planes for device connections to IN, OUT, and GND pins to optimize thermal performance | 23 |
CAD (KiCad official)
- Symbol:
TLV76750QWDRBRQ1 - Footprint:
Package_SON:WSON-8-1EP_3x3mm_P0.5mm_EP1.6x2.0mm - 3D model: WSON-8-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
tlv76750qwdrbrq1-etched.step/tlv76750qwdrbrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlv76750qwdrbrq1.step/tlv76750qwdrbrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (30 pp, sha256
54f04f3d1fecd248, retrieved 2026-11-05, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).