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TLV76750DRVR

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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, WSON-6(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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docs tlv76750drvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers tlv76750drvr: viewers · Ray 1mo ago
package.json tlv76750drvr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
page.json tlv76750drvr: specified limits as data (metadata.characteristics, 46 rows from the datasheet) · Ray 25d ago
README.md tlv76750drvr: specified limits as data (metadata.characteristics, 46 rows from the datasheet) · Ray 25d ago
tlv76750drvr-etched.fit.json tlv76750drvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tlv76750drvr-etched.glb tlv76750drvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tlv76750drvr-etched.step tlv76750drvr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tlv76750drvr.glb Publish 0.1.0 · Ray 1mo ago
tlv76750drvr.kicad_mod Publish 0.1.0 · Ray 1mo ago
tlv76750drvr.kicad_sym Publish 0.1.0 · Ray 1mo ago
tlv76750drvr.lbr Publish 0.1.0 · Ray 1mo ago
tlv76750drvr.step Publish 0.1.0 · Ray 1mo ago

TLV76750DRVR

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · WSON-6(2x2)

TLV76750DRVR from Texas Instruments, in a WSON-6(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT power_out Output pin. Use the recommended capacitor value as listed in the Recommended Operating Conditions table. Place the output capacitor as close to the OUT and GND pins of the device as possible.
2 SNS input Output sense pin. Connect the SNS pin to the OUT pin, or to remotely sense the output voltage at the load, connect the SNS pin to the load. Do not float this pin. For fixed-voltage version devices only.
3 GND power_in Ground pin. All ground pins must be grounded.
4 EN input Enable pin. Driving the enable pin high enables the device. Driving this pin low disables the device. High and low thresholds are listed in the Electrical Characteristics table. This pin has an internal pullup and can be left floating to enable the device or the pin can be connected to the input pin.
5 GND power_in Ground pin. All ground pins must be grounded.
6 IN power_in Input pin. Use the recommended capacitor value as listed in the Recommended Operating Conditions table. Place the input capacitor as close to the IN and GND pins of the device as possible.
7 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WSON-6(2x2)
Category Power Management (PMIC)
Pins 7

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage VIN -0.3 18 V All voltages with respect to GND 5
Output voltage VOUT -0.3 V Max = VIN + 0.3 V or 18 V, whichever is smaller; with respect to GND 5
Output sense voltage VSNS -0.3 V Max = VIN + 0.3 V or 18 V, whichever is smaller; with respect to GND (fixed version SNS pin) 5
Enable voltage VEN -0.3 18 V With respect to GND 5
Operating junction temperature TJ -50 150 °C 5
Storage temperature TSTG -65 150 °C 5
ESD Human body model V(ESD) -3000 3000 V HBM per ANSI/ESDA/JEDEC JS-001, all pins 5
ESD Charged device model V(ESD) -1000 1000 V CDM per JEDEC JESD22-C101, all pins 5
Input voltage VIN 2.5 16 V 5
Enable voltage VEN 0 16 V 5
Output voltage VOUT 0.8 14.6 V Shared adjustable range; fixed 5.0 V option lies within 5
Output current (2.5 V ≤ VIN < 3 V) IOUT 0 0.8 A 2.5 V ≤ VIN < 3 V 5
Output current (VIN ≥ 3 V) IOUT 0 1 A VIN ≥ 3 V 5
Output capacitor COUT 1 2.2 220 µF Effective output capacitance of 0.5 µF minimum required for stability (footnote 1) 5
Output capacitor ESR COUT ESR 2 500 mΩ 5
Input capacitor CIN 1 µF 5
Junction temperature TJ -40 125 °C 5
Junction-to-ambient thermal resistance RθJA 77.7 °C/W DRV (WSON) 6-pin package 6
Junction-to-case (top) thermal resistance RθJC(top) 92.3 °C/W DRV (WSON) 6-pin package 6
Junction-to-board thermal resistance RθJB 40.8 °C/W DRV (WSON) 6-pin package 6
Junction-to-top characterization parameter ΨJT 4.3 °C/W DRV (WSON) 6-pin package 6
Junction-to-board characterization parameter ΨJB 40.8 °C/W DRV (WSON) 6-pin package 6
Junction-to-case (bottom) thermal resistance RθJC(bot) 18.9 °C/W DRV (WSON) 6-pin package 6
Nominal output accuracy VOUT -0.5 0.5 % TJ = 25°C 6
Output accuracy over temperature VOUT -1 1 % VIN ≥ 3.0 V, 1 mA ≤ IOUT ≤ 1 A 6
Output current limit ICL 1.1 1.6 A VOUT = 0.9 x VOUT(NOM), VIN ≥ 3.0 V 6
Output current limit ICL 0.81 1.6 A VOUT = 0.9 x VOUT(NOM), 2.5 V ≤ VIN < 3.0 V 6
Short-circuit current limit ISC 150 250 350 mA VOUT = 0 V, DRV package 6
Quiescent current (fixed output devices) IQ 60 95 µA Fixed output devices, IOUT = 0 mA 6
Shutdown current ISHUTDOWN 1.5 3 µA VEN ≤ 0.4 V, VIN = 16 V 6
Dropout voltage (DRV package) VDO 0.9 1.4 V VIN ≥ 3.0 V, IOUT = 1 A, DRV package 6
Dropout voltage VDO 0.8 1.3 V 2.5 V ≤ VIN < 3.0 V, IOUT = 800 mA 6
Load regulation ΔVOUT(ΔIOUT) 0.1 0.5 %/A 1 mA ≤ IOUT ≤ 1 A, VIN ≥ 3.0 V 6
Line regulation ΔVOUT(ΔVIN) 0.02 %/V VOUT(NOM) +1.5 V ≤ VIN ≤ 16 V, IOUT = 10 mA 6
Ground current IGND 1.5 mA IOUT = 1 A, VIN ≥ 3.0 V 6
UVLO threshold rising VUVLO+ 2.2 2.4 V VIN rising 6
UVLO threshold falling VUVLO- 1.9 V VIN falling 7
UVLO hysteresis VUVLO(HYS) 130 mV 7
Thermal shutdown temperature TSD(shutdown) 180 °C Temperature increasing 7
Thermal shutdown reset temperature TSD(reset) 160 °C Temperature falling 7
Enable pin logic high VEN(HIGH) 1.2 V 2.5 V ≤ VIN ≤ 16 V 6
Enable pin logic low VEN(LOW) 0.4 V 2.5 V ≤ VIN ≤ 16 V 6
Enable pullup current IEN 400 nA VEN = 0 V 6
Output pulldown current IPULLDOWN 1.2 mA VIN = 16 V, VOUT = 2.5 V, VEN = 0 V 6
Power-supply rejection ratio PSRR 70 dB VIN = 3.3 V, VOUT = 1.8 V, IOUT = 300 mA, f = 120 Hz 6
Output noise voltage Vn 60 µVRMS BW = 10 Hz to 100 kHz, VIN = 3.3 V, VOUT = 0.8 V, IOUT = 100 mA 6

CAD (KiCad official)

  • Symbol: TLV76750DRVR
  • Footprint: Package_SON:WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm
  • 3D model: WSON-6(2x2) (KiCad packages3D, STEP)
  • 3D model files: tlv76750drvr-etched.step / tlv76750drvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlv76750drvr.step / tlv76750drvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (45 pp, sha256 c631d45696a7ef20, retrieved 2026-09-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF